hw: Added fpga vregfile #101
Annotations
2 errors and 9 warnings
lint-sv
Process completed with exit code 1.
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gitlab-ci
Process completed with exit code 1.
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lint-license
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3, actions/setup-python@v2. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
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lint-license
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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[verible-verilog-lint] hw/ip/spatz/src/vregfile_fpga.sv#L7:
hw/ip/spatz/src/vregfile_fpga.sv#L7
Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
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lint-sv
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
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gitlab-ci
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3, actions/setup-python@v4. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
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[verible-verilog-lint] hw/ip/spatz/src/vregfile_fpga.sv#L7:
hw/ip/spatz/src/vregfile_fpga.sv#L7
Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
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[verible-verilog-lint] hw/ip/spatz/src/vregfile_fpga.sv#L7:
hw/ip/spatz/src/vregfile_fpga.sv#L7
Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
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[verible-verilog-lint] hw/ip/spatz/src/vregfile_fpga.sv#L7:
hw/ip/spatz/src/vregfile_fpga.sv#L7
Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
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[verible-verilog-lint] hw/ip/spatz/src/vregfile_fpga.sv#L7:
hw/ip/spatz/src/vregfile_fpga.sv#L7
Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
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