hw: Add native bootrom

Bender.yml

@@ -159,6 +159,7 @@ sources:
       - hw/snitch_cluster/src/snitch_fpu.sv
       - hw/snitch_cluster/src/snitch_sequencer.sv
       - hw/snitch_cluster/src/snitch_tcdm_interconnect.sv
+      - target/snitch_cluster/test/snitch_bootrom.sv
       # Level 1
       - hw/snitch_cluster/src/snitch_barrier.sv
       - hw/snitch_cluster/src/snitch_fp_ss.sv

docs/schema/snitch_cluster.schema.json

@@ -16,7 +16,7 @@
         },
         "boot_addr": {
             "type": "number",
-            "description": "Address from which all harts of the cluster start to boot. The default setting is `0x8000_0000`.",
+            "description": "Address from which all harts of the cluster start to boot. The default setting is `0x8000_0000`. Unused if `alias_region_enable` is set.",
             "default": 2147483648
         },
         "cluster_base_addr": {
@@ -89,6 +89,14 @@
                 64
             ]
         },
+        "bootrom_size": {
+            "type": "number",
+            "description": "Address region size reserved for the Bootrom-Memory in KiByte.",
+            "examples": [
+                128,
+                64
+            ]
+        },
         "alias_region_enable": {
             "type": "boolean",
             "description": "Whether to provide a hardwired alias region for the TCDM (and cluster) address space.",

hw/snitch/src/snitch_pkg.sv

@@ -139,7 +139,8 @@ package snitch_pkg;
   typedef enum int unsigned {
     TCDMDMA    = 0,
     SoCDMAOut  = 1,
-    ZeroMemory = 2
+    ZeroMemory = 2,
+    BootRom    = 3
   } cluster_slave_dma_e;
 
   typedef enum int unsigned {

hw/snitch_cluster/src/snitch_cluster.sv

@@ -37,7 +37,8 @@ module snitch_cluster
   parameter int unsigned NarrowUserWidth    = 1,
   /// AXI: dma user width.
   parameter int unsigned WideUserWidth      = 1,
-  /// Address from which to fetch the first instructions.
+  /// Boot Address from which to fetch the first instructions.
+  /// Only used if `AliasRegionEnable` is not set.
   parameter logic [31:0] BootAddr           = 32'h0,
   /// Number of Hives. Each Hive can hold 1-many cores.
   parameter int unsigned NrHives            = 1,
@@ -47,6 +48,8 @@ module snitch_cluster
   parameter int unsigned TCDMDepth          = 1024,
   /// Zero memory address region size (in kB).
   parameter int unsigned ZeroMemorySize     = 64,
+  /// Bootrom memory address region size (in kB).
+  parameter int unsigned BootRomSize        = 4,
   /// Cluster peripheral address region size (in kB).
   parameter int unsigned ClusterPeriphSize  = 64,
   /// Number of TCDM Banks. It is recommended to have twice the number of banks
@@ -280,7 +283,7 @@ module snitch_cluster
   localparam int unsigned NrWideMasters = 1 + DMANumChannels + NrHives;
   localparam int unsigned WideIdWidthOut = $clog2(NrWideMasters) + WideIdWidthIn;
   // DMA X-BAR configuration
-  localparam int unsigned NrWideSlaves = 3;
+  localparam int unsigned NrWideSlaves = 4;
   localparam int unsigned NrWideRuleIdcs = NrWideSlaves - 1;
   localparam int unsigned NrWideRules = (1 + AliasRegionEnable) * NrWideRuleIdcs;
 
@@ -463,6 +466,10 @@ module snitch_cluster
   assign cluster_periph_start_address = tcdm_end_address;
   assign cluster_periph_end_address   = tcdm_end_address + ClusterPeriphSize * 1024;
 
+  addr_t bootrom_start_address, bootrom_end_address;
+  assign bootrom_start_address = cluster_periph_start_address + 4 * 1024;
+  assign bootrom_end_address   = cluster_periph_end_address;
+
   addr_t zero_mem_start_address, zero_mem_end_address;
   assign zero_mem_start_address = cluster_periph_end_address;
   assign zero_mem_end_address   = cluster_periph_end_address + ZeroMemorySize * 1024;
@@ -473,9 +480,13 @@ module snitch_cluster
   localparam addr_t PeriphAliasStart = TCDMAliasEnd;
   localparam addr_t PeriphAliasEnd   = TCDMAliasEnd + ClusterPeriphSize * 1024;
 
+  localparam addr_t BootRomAliasStart = PeriphAliasStart + 4 * 1024;
+  localparam addr_t BootRomAliasEnd   = PeriphAliasEnd;
+
   localparam addr_t ZeroMemAliasStart = PeriphAliasEnd;
   localparam addr_t ZeroMemAliasEnd   = PeriphAliasEnd + ZeroMemorySize * 1024;
 
+
   // ----------------
   // Wire Definitions
   // ----------------
@@ -585,6 +596,11 @@ module snitch_cluster
       idx:        ZeroMemory,
       start_addr: zero_mem_start_address,
       end_addr:   zero_mem_end_address
+    },
+    '{
+      idx:        BootRom,
+      start_addr: bootrom_start_address,
+      end_addr:   bootrom_end_address
     }
   };
   if (AliasRegionEnable) begin : gen_dma_xbar_alias
@@ -598,6 +614,11 @@ module snitch_cluster
         idx:        ZeroMemory,
         start_addr: ZeroMemAliasStart,
         end_addr:   ZeroMemAliasEnd
+      },
+      '{
+        idx:        BootRom,
+        start_addr: BootRomAliasStart,
+        end_addr:   BootRomAliasEnd
       }
     };
   end
@@ -857,6 +878,8 @@ module snitch_cluster
 
       tcdm_req_t [TcdmPorts-1:0] tcdm_req_wo_user;
 
+      parameter logic [31:0] BootAddrInternal = AliasRegionEnable ? BootRomAliasStart : BootAddr;
+
       snitch_cc #(
         .AddrWidth (PhysicalAddrWidth),
         .DataWidth (NarrowDataWidth),
@@ -881,7 +904,7 @@ module snitch_cluster
         .acc_req_t (acc_req_t),
         .acc_resp_t (acc_resp_t),
         .dma_events_t (dma_events_t),
-        .BootAddr (BootAddr),
+        .BootAddr (BootAddrInternal),
         .RVE (RVE[i]),
         .RVF (RVF[i]),
         .RVD (RVD[i]),
@@ -1236,6 +1259,37 @@ module snitch_cluster
     .reg_rsp_i (reg_rsp)
   );
 
+  addr_t bootrom_addr;
+  data_dma_t bootrom_data, bootrom_data_q;
+  logic bootrom_req,  bootrom_req_q;
+
+  `FF(bootrom_data_q, bootrom_data, '0, clk_i, rst_ni)
+  `FF(bootrom_req_q,  bootrom_req,  '0, clk_i, rst_ni)
+
+  axi_to_mem #(
+    .axi_req_t (axi_slv_dma_req_t),
+    .axi_resp_t (axi_slv_dma_resp_t),
+    .AddrWidth (PhysicalAddrWidth),
+    .DataWidth (WideDataWidth),
+    .IdWidth (WideIdWidthOut),
+    .NumBanks (1)
+  ) i_axi_to_mem (
+    .clk_i (clk_i),
+    .rst_ni (rst_ni),
+    .busy_o (),
+    .axi_req_i (wide_axi_slv_req[BootRom]),
+    .axi_resp_o (wide_axi_slv_rsp[BootRom]),
+    .mem_req_o (bootrom_req),
+    .mem_gnt_i (bootrom_req),
+    .mem_addr_o (bootrom_addr),
+    .mem_wdata_o (),
+    .mem_strb_o (),
+    .mem_atop_o (),
+    .mem_we_o (),
+    .mem_rvalid_i (bootrom_req_q),
+    .mem_rdata_i (bootrom_data_q)
+  );
+
   snitch_cluster_peripheral #(
     .reg_req_t (reg_req_t),
     .reg_rsp_t (reg_rsp_t),
@@ -1256,6 +1310,17 @@ module snitch_cluster
     .icache_events_i (icache_events)
   );
 
+  snitch_bootrom #(
+    .AddrWidth (PhysicalAddrWidth),
+    .DataWidth (WideDataWidth),
+    .BootromSize (BootRomSize * 1024)
+  ) i_bootrom (
+    .clk_i (clk_i),
+    .rst_ni (rst_ni),
+    .addr_i (bootrom_addr),
+    .data_o (bootrom_data)
+  );
+
   // Optionally decouple the external narrow AXI master ports.
   axi_cut #(
     .Bypass     ( !RegisterExtNarrow ),

hw/snitch_cluster/src/snitch_cluster_peripheral/Makefile

@@ -0,0 +1,27 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Noah Huetter <[email protected]>
+
+BENDER=$(shell which bender)
+REGTOOL=$(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
+PYTHON3=$(shell which python)
+CLANG_FORMAT=$(shell which clang-format-12.0.1)
+
+SCHEMA=snitch_cluster_peripheral_reg.hjson
+
+PKG=snitch_cluster_peripheral_reg_pkg.sv
+TOP=snitch_cluster_peripheral_reg_top.sv
+CDEF=../../../../target/snitch_cluster/sw/runtime/common/snitch_cluster_peripheral.h
+
+all: $(PKG) $(TOP) $(CDEF)
+
+$(PKG): $(SCHEMA)
+	$(PYTHON3) $(REGTOOL) -r -t $(dir $@) $<
+$(TOP): $(SCHEMA)
+	$(PYTHON3) $(REGTOOL) -r -t $(dir $@) $<
+
+%.h: $(SCHEMA)
+	$(PYTHON3) $(REGTOOL) -D -o $@ $<
+	$(CLANG_FORMAT) -i $@

hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson

@@ -4,11 +4,18 @@
 // Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details.
 {
     param_list: [
-        { name: "NumPerfCounters",
+        {
+        name: "NumPerfCounters",
         desc: "Number of performance counters",
         type: "int",
         default: "16"
         },
+        {
+        name: "NumCtrlScratch",
+        desc: "Number of scratch registers",
+        type: "int",
+        default: "4"
+        },
     ],
     name: "snitch_cluster_peripheral",
     clock_primary: "clk_i",
@@ -303,6 +310,22 @@
             }]
         }
     },
+    {
+        multireg: {
+            name: "SCRATCH",
+            desc: '''Scratch registers. Used in the bootrom for various purposes.'''
+            swaccess: "rw",
+            hwaccess: "none",
+            count: "NumCtrlScratch",
+            cname: "ctrl_scratch",
+            compact: "false",
+            fields: [{
+                bits: "31:0",
+                name: "SCRATCH",
+                desc: "Scratch register"
+            }]
+        }
+    },
     {
         name: "CL_CLINT_SET",
         desc: '''

hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv

@@ -8,6 +8,7 @@ package snitch_cluster_peripheral_reg_pkg;
 
   // Param list
   parameter int NumPerfCounters = 16;
+  parameter int NumCtrlScratch = 4;
 
   // Address widths within the block
   parameter int BlockAw = 9;
@@ -128,9 +129,13 @@ package snitch_cluster_peripheral_reg_pkg;
   parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13_OFFSET = 9'h 168;
   parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14_OFFSET = 9'h 170;
   parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET = 9'h 178;
-  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 180;
-  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 188;
-  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 190;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0_OFFSET = 9'h 180;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET = 9'h 188;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2_OFFSET = 9'h 190;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3_OFFSET = 9'h 198;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 1a0;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 1a8;
+  parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 1b0;
 
   // Reset values for hwext registers and their fields
   parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_RESVAL = 32'h 0;
@@ -218,13 +223,17 @@ package snitch_cluster_peripheral_reg_pkg;
     SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13,
     SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14,
     SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15,
+    SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0,
+    SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1,
+    SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2,
+    SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3,
     SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET,
     SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR,
     SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
   } snitch_cluster_peripheral_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [51] = '{
+  parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [55] = '{
     4'b 0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0
     4'b 0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1
     4'b 0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2
@@ -273,9 +282,13 @@ package snitch_cluster_peripheral_reg_pkg;
     4'b 1111, // index[45] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_13
     4'b 1111, // index[46] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_14
     4'b 1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15
-    4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET
-    4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR
-    4'b 0001  // index[50] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
+    4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_0
+    4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1
+    4'b 1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_2
+    4'b 1111, // index[51] SNITCH_CLUSTER_PERIPHERAL_SCRATCH_3
+    4'b 1111, // index[52] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET
+    4'b 1111, // index[53] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR
+    4'b 0001  // index[54] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
   };
 
 endpackage