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hw: Add native bootrom #168

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9a9f210
Chagned makro names
Apr 4, 2024
86dae13
Setup Bootrom Generation.
May 14, 2024
26774f8
Bootable Bootrom instantiated.
May 14, 2024
8598be9
Setup Bootrom Generation.
MilosHirsl Apr 3, 2024
bada8fa
Bootable Bootrom instantiated.
MilosHirsl Apr 18, 2024
de56699
Linked Bootrom Scratch Register to correct address.
MilosHirsl May 3, 2024
37f73fc
Fixed Scratch Register linking address. Modified regfile for synthesis.
MilosHirsl May 3, 2024
e4e1a82
Modified bootrom to avoid synthesis issues.
MilosHirsl May 8, 2024
aae8b77
Moved Bootrom Space into Cluster Peripheral.
MilosHirsl May 15, 2024
84b2b9a
Changed Scratch Registers Software Permissions to allow Read/Write an…
MilosHirsl May 16, 2024
a59c0d5
Adjusted assignment size from generated boot data to actual boot size.
MilosHirsl May 20, 2024
3f0b447
Fixed assign statement.
MilosHirsl May 20, 2024
6080ca4
Modified bootrom after debugging to fetch address at scratch register 1.
MilosHirsl May 24, 2024
01bb61b
git: Remove unused config file
fischeti Jul 18, 2024
dea6c44
hw: Don't change reset value of performance counters
fischeti Jul 18, 2024
522e744
hw: Fix peripheral reg Makefile
fischeti Jul 18, 2024
cfc0bec
git: Remove original files
fischeti Jul 18, 2024
156aaf1
bootrom: Remove old script
fischeti Jul 18, 2024
ff98472
hw: Clean up bootrom generation
fischeti Jul 18, 2024
19208ea
util: Move bootrom generation script to util folder
fischeti Jul 18, 2024
94e6c7d
Clean up some more
fischeti Jul 18, 2024
630b8fc
lint: Python files
fischeti Jul 18, 2024
7d2e55c
lint: Fix missing license headers
fischeti Jul 18, 2024
1148172
lint: Other formatting
fischeti Jul 18, 2024
069fbef
hw: Rename `bootrom` to `snitch_bootrom`
fischeti Jul 18, 2024
96ffb68
hw: Format auto-generated SV sources
fischeti Jul 18, 2024
492491f
Revert "hw: Format auto-generated SV sources"
fischeti Jul 18, 2024
2e860eb
hw: Rename scratch registers and disable `hwext` setting
fischeti Jul 18, 2024
11b93a6
bootrom: Enable external interrupts
fischeti Jul 18, 2024
afb447f
test: Write binary entry point from testbench to scratch1 register
fischeti Jul 18, 2024
1982782
lint: C++ sources
fischeti Jul 19, 2024
8c8114e
hw: Fix unused parameters in `axi_to_mem`
fischeti Jul 19, 2024
5656e4a
test: Use simpler AXI driver for compatibility with verilator
fischeti Jul 19, 2024
15a1a87
test: Use simple bootrom that directly jumps to L3
fischeti Jul 22, 2024
20eed23
cfg: Don't specify `boot_addr`
fischeti Jul 22, 2024
9afc478
cfg: Specify `boot_rom_size` for all configurations
fischeti Jul 22, 2024
0179bf7
doc: Update `boot_addr` description
fischeti Jul 22, 2024
6b3fb12
hw: Rename `BootOrigin` to `BootAddrInternal`
fischeti Jul 22, 2024
f19d7b0
misc: Revert unused stuff
fischeti Jul 22, 2024
be60cd7
vlt: Remove `bootrom.cc`
fischeti Jul 22, 2024
80c5a11
banshee: Update addresses
fischeti Jul 22, 2024
f23d563
tb: Revert small changes
fischeti Jul 22, 2024
775afb8
bootrom: Don't write author list in auto-generated SV file
fischeti Jul 22, 2024
36f02c3
misc: Fix comments and formatting
fischeti Jul 23, 2024
d2291f5
Revert "Chagned makro names"
fischeti Jul 23, 2024
e081027
cfg: Update `dma_mchan` config
fischeti Aug 1, 2024
0dc5db1
cfg: Remove unused `boot_addr` in configs
fischeti Aug 5, 2024
38cb133
cfg: Remove obsolete quadrant config
fischeti Aug 5, 2024
077ac88
cfg: Add `boot_rom_size` config
fischeti Aug 5, 2024
d3513f9
cfg: Rename `boot_rom_size` to `bootrom_size`
fischeti Aug 5, 2024
e14744e
hw: Add bootrom generation to `rtl` target
fischeti Aug 29, 2024
dae7047
hw: Update sources
fischeti Aug 29, 2024
81309c1
bootrom: Use clang to compile bootrom
fischeti Aug 29, 2024
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test: Use simpler AXI driver for compatibility with verilator
fischeti committed Aug 29, 2024
commit 5656e4af6e0a8b573a8f78207898f2278a73b82b
66 changes: 27 additions & 39 deletions target/snitch_cluster/test/testharness.sv
Original file line number Diff line number Diff line change
@@ -78,45 +78,26 @@ module testharness import snitch_cluster_pkg::*; (
.rsp_o (wide_out_resp)
);

AXI_BUS_DV #(
.AXI_ADDR_WIDTH ( AddrWidth ),
.AXI_DATA_WIDTH ( NarrowDataWidth ),
.AXI_ID_WIDTH ( NarrowIdWidthIn ),
.AXI_USER_WIDTH ( NarrowUserWidth )
) narrow_in (clk_i);

`AXI_ASSIGN_TO_REQ(narrow_in_req, narrow_in)
`AXI_ASSIGN_FROM_RESP(narrow_in, narrow_in_resp)

typedef axi_test::axi_driver #(
.AW ( AddrWidth ),
.DW ( NarrowDataWidth ),
.IW ( NarrowIdWidthIn ),
.UW ( NarrowUserWidth )
) narrow_drv_t;

narrow_drv_t narrow_drv_in = new(narrow_in);


task automatic narrow_write(
task narrow_write(
input logic [AddrWidth-1:0] addr,
input logic [NarrowDataWidth-1:0] data
input logic [NarrowDataWidth-1:0] data,
output axi_pkg::resp_t resp
);
automatic narrow_drv_t::ax_beat_t ax = new();
automatic narrow_drv_t::w_beat_t w = new();
automatic narrow_drv_t::b_beat_t b;
@(posedge clk_i);
ax.ax_addr = addr;
ax.ax_id = '0;
ax.ax_len = '0;
ax.ax_size = $clog2(NarrowDataWidth/8);
ax.ax_burst = axi_pkg::BURST_INCR;
narrow_drv_in.send_aw(ax);
w.w_strb = '1;
w.w_data = data;
w.w_last = 1'b1;
narrow_drv_in.send_w(w);
narrow_drv_in.recv_b(b);
narrow_in_req.aw.addr = addr;
narrow_in_req.aw.size = $clog2(NarrowDataWidth/8);
narrow_in_req.aw.burst = axi_pkg::BURST_INCR;
narrow_in_req.aw_valid = 1'b1;
do @(posedge clk_i); while (!narrow_in_resp.aw_ready);
narrow_in_req.aw_valid = 1'b0;
narrow_in_req.w.data = data;
narrow_in_req.w.strb = '1;
narrow_in_req.w_valid = 1'b1;
do @(posedge clk_i); while (!narrow_in_resp.w_ready);
narrow_in_req.w_valid = 1'b0;
narrow_in_req.b_ready = 1'b1;
do @(posedge clk_i); while (!narrow_in_resp.b_valid);
resp = narrow_in_resp.b.resp;
narrow_in_req.b_ready = 1'b0;
endtask

localparam int unsigned PeriphBaseAddr = snitch_cluster_pkg::CfgClusterBaseAddr +
@@ -125,13 +106,20 @@ module testharness import snitch_cluster_pkg::*; (
snitch_cluster_peripheral_reg_pkg::SNITCH_CLUSTER_PERIPHERAL_SCRATCH_1_OFFSET;

initial begin
axi_pkg::resp_t resp;
meip = '0;
narrow_in_req = '0;
narrow_in_req.aw.burst = axi_pkg::BURST_INCR;
narrow_in_req.ar.burst = axi_pkg::BURST_INCR;
narrow_in_req.aw.cache = axi_pkg::CACHE_MODIFIABLE;
narrow_in_req.ar.cache = axi_pkg::CACHE_MODIFIABLE;
@(negedge rst_ni);
narrow_drv_in.reset_master();
// Wait for some time
#300ns;
// Write to the scratch1 register
narrow_write(Scratch1Addr, get_bin_entry());
@(posedge clk_i);
narrow_write(Scratch1Addr, get_bin_entry(), resp);
assert(resp == axi_pkg::RESP_OKAY);
$display("[NarrowAxi] Writing entry point %x to scratch1", get_bin_entry());
// Assert the external interrupt for a single cycle
// to start the cores