Eliminated Non-Resettable FFs.

FindNonResettableFFs.py

@@ -0,0 +1,27 @@
+import os
+
+text = 'amo_op_e'
+path = '/scratch/bsc24f10/Documents/MonocerosGithubRepo/monoceros/snitch_cluster/hw'
+
+def searchText(path):
+
+	os.chdir(path)
+	files = os.listdir(path)
+	#print(files)
+
+	for file_name in files:
+		abs_path = os.path.join(path, file_name)
+		#print('is '+ abs_path + ' directory? : ')
+		if os.path.isdir(abs_path):
+			#print("Directory found: " + abs_path)
+			searchText(abs_path)
+
+		if os.path.isfile(abs_path):
+			#print("File found: " + abs_path)
+			with open(abs_path, 'r') as f:
+				if text in f.read():
+					final_path = os.path.abspath(file_name)
+					print(text + " word found in this path " + final_path)
+	pass
+searchText(path)
+print("DONE")

hw/reqrsp_interface/src/axi_to_reqrsp.sv

@@ -371,12 +371,12 @@ module axi_to_reqrsp #(
   };
 
   // Registers
-  `FFARN(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni)
-  `FFARN(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni)
-  `FFARN(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni)
-  `FFARN(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni)
-  `FFARN(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni)
-  `FFARN(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni)
+  `FF(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni)
+  `FF(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni)
+  `FF(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni)
+  `FF(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni)
+  `FF(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni)
+  `FF(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni)
 
   // Assertions
   // Make sure that write is never set for AMOs.

hw/snitch/src/snitch.sv

@@ -282,10 +282,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   logic [31:0] dscratch_d, dscratch_q;
   logic debug_d, debug_q;
 
-  `FFNR(scratch_q, scratch_d, clk_i)
-  `FFNR(tvec_q, tvec_d, clk_i)
-  `FFNR(epc_q, epc_d, clk_i)
-  `FFNR(satp_q, satp_d, clk_i)
+  `FFAR(scratch_q, scratch_d, '0, clk_i, rst_i)
+  `FFAR(tvec_q, tvec_d, '0, clk_i, rst_i)
+  `FFAR(epc_q, epc_d, '0, clk_i, rst_i)
+  `FFAR(satp_q, satp_d, '0, clk_i, rst_i)
   `FFAR(cause_q, cause_d, '0, clk_i, rst_i)
   `FFAR(cause_irq_q, cause_irq_d, '0, clk_i, rst_i)
   `FFAR(priv_lvl_q, priv_lvl_d, snitch_pkg::PrivLvlM, clk_i, rst_i)
@@ -305,8 +305,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
 
   if (DebugSupport) begin : gen_debug
     `FFAR(dcsr_q, dcsr_d, '0, clk_i, rst_i)
-    `FFNR(dpc_q, dpc_d, clk_i)
-    `FFNR(dscratch_q, dscratch_d, clk_i)
+    `FFAR(dpc_q, dpc_d, '0, clk_i, rst_i)
+    `FFAR(dscratch_q, dscratch_d, '0, clk_i, rst_i)
     `FFAR(debug_q, debug_d, '0, clk_i, rst_i) // Debug mode
   end else begin : gen_no_debug
     assign dcsr_q = '0;
@@ -2630,6 +2630,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     .ADDR_WIDTH     ( RegWidth )
   ) i_snitch_regfile (
     .clk_i,
+    .rst_ni    ( ~rst_i    ),
     .raddr_i   ( gpr_raddr ),
     .rdata_o   ( gpr_rdata ),
     .waddr_i   ( gpr_waddr ),

hw/snitch/src/snitch_l0_tlb.sv

@@ -2,9 +2,11 @@
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 
-`include "common_cells/registers.svh"
 // Author: Florian Zaruba <[email protected]>
 
+`include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
+
 // MMU w/ L0 TLB
 module snitch_l0_tlb import snitch_pkg::*; #(
   parameter int unsigned NrEntries = 1,
@@ -66,8 +68,8 @@ module snitch_l0_tlb import snitch_pkg::*; #(
   l0_pte_t pte;
 
   `FFAR(tag_valid_q, tag_valid_d, '0, clk_i, rst_i)
-  `FFNR(tag_q, tag_d, clk_i)
-  `FFNR(pte_q, pte_d, clk_i)
+  `FFAR(tag_q, tag_d, '0, clk_i, rst_i)
+  `FFAR(pte_q, pte_d, '0, clk_i, rst_i)
 
   logic [NrEntries-1:0] hit;
   logic miss_d, miss_q; // we got a miss

hw/snitch/src/snitch_regfile_ff.sv

@@ -14,6 +14,7 @@ module snitch_regfile #(
 ) (
   // clock and reset
   input  logic                                      clk_i,
+  input  logic                                      rst_ni,
   // read port
   input  logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0]  raddr_i,
   output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0]  rdata_o,
@@ -38,19 +39,23 @@ module snitch_regfile #(
       end
     end
 
-    // loop from 1 to NumWords-1 as R0 is nil
-    always_ff @(posedge clk_i) begin : register_write_behavioral
-      for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
-        for (int unsigned i = 0; i < NumWords; i++) begin
+  // loop from 1 to NumWords-1 as R0 is nil
+  always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral
+    for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
+      for (int unsigned i = 0; i < NumWords; i++) begin
+        if (~rst_ni) begin
+          mem[i] <= '0;
+        end else begin
           if (we_dec[j][i]) begin
             mem[i] <= wdata_i[j];
           end
         end
-        if (ZERO_REG_ZERO) begin
-          mem[0] <= '0;
-        end
+      end
+      if (ZERO_REG_ZERO) begin
+        mem[0] <= '0;
       end
     end
+  end
 
   for (genvar i = 0; i < NR_READ_PORTS; i++) begin : gen_read_port
     assign rdata_o[i] = mem[raddr_i[i]];

hw/snitch/src/snitch_regfile_fpga.sv

@@ -30,6 +30,7 @@ module snitch_regfile #(
 )(
   // clock and reset
   input  logic                                      clk_i,
+  input  logic                                      rst_ni,
   // read port
   input  logic [NR_READ_PORTS-1:0][4:0]             raddr_i,
   output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0]  rdata_o,
@@ -83,18 +84,12 @@ module snitch_regfile #(
   end
 
   // block selector flops
-  always_ff @(posedge clk_i) begin
-    mem_block_sel_q <= mem_block_sel;
-  end
+  `FF(mem_block_sel_q, mem_block_sel, '0, clk_i, rst_ni)
 
   // distributed RAM blocks
   logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [NR_WRITE_PORTS];
   for (genvar j=0; j<NR_WRITE_PORTS; j++) begin : gen_regfile_ram_block
-    always_ff @(posedge clk_i) begin
-      if (we_i[j]) begin
-        mem[j][waddr_i[j]] <= wdata_i[j];
-      end
-    end
+    `FFL(mem[j][waddr_i[j]], wdata_i[j], we_i[j], '0, clk_i, rst_ni)
     for (genvar k=0; k<NR_READ_PORTS; k++) begin : gen_block_read
       assign mem_read[j][k] = mem[j][raddr_i[k]];
     end

hw/snitch/src/snitch_regfile_latch.sv

@@ -14,6 +14,7 @@ module snitch_regfile #(
 ) (
   // clock and reset
   input  logic                                      clk_i,
+  input  logic                                      rst_ni,
   // read port
   input  logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0]  raddr_i,
   output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0]  rdata_o,
@@ -49,7 +50,8 @@ module snitch_regfile #(
 
   // Sample Input Data
   for (genvar i = 0; i < NR_WRITE_PORTS; i++) begin : gen_data_ports
-    always_ff @(posedge clk) wdata_q[i] <= wdata_i[i];
+
+    `FF(wdata_q[i], wdata_i[i], '0, clk, rst_ni)
 
     for (genvar j = ZERO_REG_ZERO; j < NumWords; j++) begin : gen_data_words
       always_comb begin

hw/snitch_cluster/src/snitch_amo_shim.sv

@@ -189,12 +189,12 @@ module snitch_amo_shim
   assign wdata = $unsigned(wdata_i);
 
   `FF(state_q, state_d, Idle)
-  `FFLNR(amo_op_q, amo_i, load_amo, clk_i)
-  `FFLNR(addr_q, addr_i, load_amo, clk_i)
+  `FFL(amo_op_q, amo_i, load_amo, AMONone, clk_i, rst_ni)
+  `FFL(addr_q, addr_i, load_amo, '0, clk_i, rst_ni)
   // Which word to pick.
-  `FFLNR(idx_q, idx_d, load_amo, clk_i)
-  `FFLNR(operand_b_q, (wstrb_i[0] ? wdata[31:0]  : wdata[63:32]), load_amo, clk_i)
-  `FFLNR(amo_result_q, amo_result, (state_q == DoAMO), clk_i)
+  `FFL(idx_q, idx_d, load_amo, '0, clk_i, rst_ni)
+  `FFL(operand_b_q, (wstrb_i[0] ? wdata[31:0]  : wdata[63:32]), load_amo, '0, clk_i, rst_ni)
+  `FFL(amo_result_q, amo_result, (state_q == DoAMO), '0, clk_i, rst_ni)
 
   assign idx_d = ((DataWidth == 64) ? wstrb_i[DataWidth/8/2] : 0);
   assign load_amo = valid_i & ready_o &

hw/snitch_cluster/src/snitch_clkdiv2.sv

@@ -26,10 +26,14 @@
 // Author: Florian Zaruba <[email protected]>
 // Author: Fabian Schuiki <[email protected]>
 
+`include "common_cells/registers.svh"
+`include "common_cells/assertions.svh"
+
 (* no_ungroup *)
 (* no_boundary_optimization *)
 module snitch_clkdiv2 (
   input  logic clk_i,
+  input  logic rst_ni,
   input  logic test_mode_i,
   input  logic bypass_i,
   output logic clk_o
@@ -53,7 +57,8 @@ module snitch_clkdiv2 (
   assign clk_div_del = clk_div;
   `endif
 
-  always_ff @(posedge clk_i) clk_div <= ~clk_div;
+  `FF(clk_div, ~clk_div, '0, clk_i, rst_ni)
+
   assign clk_o = (test_mode_i | bypass_i) ? clk_i : clk_div_del;
 
 endmodule

hw/snitch_cluster/src/snitch_cluster.sv

@@ -822,6 +822,7 @@ module snitch_cluster
   if (IsoCrossing) begin : gen_clk_divider
     snitch_clkdiv2 i_snitch_clkdiv2 (
       .clk_i,
+      .rst_ni (rst_ni),
       .test_mode_i (1'b0),
       .bypass_i ( clk_d2_bypass_i ),
       .clk_o (clk_d2)
@@ -1275,8 +1276,8 @@ module snitch_cluster
   // --------------------
   logic [NrTCDMPortsCores-1:0] flat_acc, flat_con;
   for (genvar i = 0; i < NrTCDMPortsCores; i++) begin  : gen_event_counter
-    `FFARN(flat_acc[i], tcdm_req[i].q_valid, '0, clk_i, rst_ni)
-    `FFARN(flat_con[i], tcdm_req[i].q_valid & ~tcdm_rsp[i].q_ready, '0, clk_i, rst_ni)
+    `FF(flat_acc[i], tcdm_req[i].q_valid, '0, clk_i, rst_ni)
+    `FF(flat_con[i], tcdm_req[i].q_valid & ~tcdm_rsp[i].q_ready, '0, clk_i, rst_ni)
   end
 
   popcount #(

hw/snitch_cluster/src/snitch_fp_ss.sv

@@ -2420,6 +2420,7 @@ module snitch_fp_ss import snitch_pkg::*; #(
     .ADDR_WIDTH     ( 5    )
   ) i_ff_regfile (
     .clk_i,
+    .rst_ni    ( ~rst_i    ),
     .raddr_i   ( fpr_raddr ),
     .rdata_o   ( fpr_rdata ),
     .waddr_i   ( fpr_waddr ),

hw/snitch_cluster/src/snitch_sequencer.sv

@@ -43,6 +43,7 @@ module snitch_sequencer import snitch_pkg::*; #(
     input  logic                             streamctl_valid_i,
     output logic                             streamctl_ready_o
 );
+
   localparam int RptBits = 16;
 
   typedef struct packed {
@@ -104,7 +105,7 @@ module snitch_sequencer import snitch_pkg::*; #(
     rb_empty = (rb_rd_pointer ^ rb_wr_pointer) == '0;
   end
 
-  `FFNR(mem_q, mem_d, clk_i)
+  `FFAR(mem_q, mem_d, '0, clk_i, rst_i)
 
   /// Compute ringbuffer addresses.
   logic [DepthBits:0] rd_pointer_d, rd_pointer_q;

hw/snitch_cluster/src/snitch_shared_muldiv.sv

@@ -196,9 +196,9 @@ module snitch_shared_muldiv_multiplier #(
   end
   `FF(valid_q, valid_d, '0)
   // Pipe-line registers
-  `FFLNR(id_q, id_i, (valid_i & ready_o), clk_i)
-  `FFLNR(result_q, result_d, (valid_i & ready_o), clk_i)
-  `FFLNR(select_upper_q, select_upper_d, (valid_i & ready_o), clk_i)
+  `FFL(id_q, id_i, (valid_i & ready_o), '0, clk_i, rst_ni)
+  `FFL(result_q, result_d, (valid_i & ready_o), '0, clk_i, rst_ni)
+  `FFL(select_upper_q, select_upper_d, (valid_i & ready_o), '0, clk_i, rst_ni)
 
   assign id_o = id_q;
   assign valid_o = valid_q;
@@ -416,32 +416,16 @@ module snitch_shared_muldiv_serdiv #(
   assign op_b_d = (b_reg_en) ? b_mux : op_b_q;
   assign res_d = (load_en) ? '0 : (res_reg_en) ? {res_q[$high(res_q)-1:0], ab_comp} : res_q;
 
-  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
-    if (!rst_ni) begin
-      state_q        <= IDLE;
-      op_a_q         <= '0;
-      op_b_q         <= '0;
-      res_q          <= '0;
-      cnt_q          <= '0;
-      id_q           <= '0;
-      rem_sel_q      <= 1'b0;
-      comp_inv_q     <= 1'b0;
-      res_inv_q      <= 1'b0;
-      op_b_zero_q    <= 1'b0;
-      div_res_zero_q <= 1'b0;
-    end else begin
-      state_q        <= state_d;
-      op_a_q         <= op_a_d;
-      op_b_q         <= op_b_d;
-      res_q          <= res_d;
-      cnt_q          <= cnt_d;
-      id_q           <= id_d;
-      rem_sel_q      <= rem_sel_d;
-      comp_inv_q     <= comp_inv_d;
-      res_inv_q      <= res_inv_d;
-      op_b_zero_q    <= op_b_zero_d;
-      div_res_zero_q <= div_res_zero_d;
-    end
-  end
+  `FF(state_q, state_d, IDLE, clk_i, rst_ni)
+  `FF(op_a_q, op_a_d, '0, clk_i, rst_ni)
+  `FF(op_b_q, op_b_d, '0, clk_i, rst_ni)
+  `FF(res_q, res_d, '0, clk_i, rst_ni)
+  `FF(cnt_q, cnt_d, '0, clk_i, rst_ni)
+  `FF(id_q, id_d, '0, clk_i, rst_ni)
+  `FF(rem_sel_q, rem_sel_d, '0, clk_i, rst_ni)
+  `FF(comp_inv_q, comp_inv_d, '0, clk_i, rst_ni)
+  `FF(res_inv_q, res_inv_d, '0, clk_i, rst_ni)
+  `FF(op_b_zero_q, op_b_zero_d, '0, clk_i, rst_ni)
+  `FF(div_res_zero_q, div_res_zero_d, '0, clk_i, rst_ni)
 
 endmodule

hw/snitch_ipu/src/snitch_int_ss.sv

@@ -601,7 +601,7 @@ module snitch_int_ss import riscv_instr::*; import snitch_ipu_pkg::*; import sni
   );
 
   for (genvar i = 0; i < 2; i++) begin : gen_multi_cycle_buffer
-    `FFLNR(imd_val_q[i], imd_val_q[i], imd_val_we[i], clk_i)
+    `FFL(imd_val_q[i], imd_val_q[i], imd_val_we[i], '0, clk_i, rst_i)
   end
 
   // ---------------
@@ -615,6 +615,7 @@ module snitch_int_ss import riscv_instr::*; import snitch_ipu_pkg::*; import sni
     .ADDR_WIDTH     ( 5  )
   ) i_ipu_regfile (
     .clk_i,
+    .rst_ni    (~rst_i),
     .raddr_i   ( int_raddr ),
     .rdata_o   ( int_rdata ),
     .waddr_i   ( int_waddr ),

hw/snitch_ssr/src/snitch_ssr.sv

@@ -110,7 +110,7 @@ module snitch_ssr import snitch_ssr_pkg::*; #(
   // When the SSR reverses direction, the inflight data *must* be vacated before any
   // requests can be issued (i.e. addresses consumed) to prevent stream corruption.
   logic agen_write_q, agen_write_reversing, agen_flush, dm_write;
-  `FFLARN(agen_write_q, agen_write, agen_valid & agen_ready, '0, clk_i, rst_ni)
+  `FFL(agen_write_q, agen_write, agen_valid & agen_ready, '0, clk_i, rst_ni)
 
   // When direction reverses, deassert agen readiness until credits replenished.
   // The datamover must preserve its directional muxing until the flush is complete.