sw: Fix snrt_dma_wait implementation (#153)

The previous implementation of `snrt_dma_wait` was incorrect as it had an infinite loop in the case that `tid` was the last completed transaction. Looking at the documentation, the snippet in custom_instructions.md shows the correct way of implementing the transaction check (get last completed tid and loop if it's less than the one we are waiting for) except it had its register operands swapped.
This PR uses that implementation instead, fixes the small bug in the documentation and changes one of the waits in `dma_simple.c` to make sure we don't regress either.

---------

Co-authored-by: Luca Colagrande <[email protected]>

docs/rm/custom_instructions.md

@@ -104,7 +104,7 @@ The DMSTATI instruction can be used to implement a blocking wait for the complet
 
         dmcpyi a0, ...
     1:  dmstati t0, 0
-        bltu a0, t0, 1b
+        bltu t0, a0, 1b
 
 Similarly, waiting for the completion of *all* DMA transfers:
 

sw/snRuntime/src/dma.h

@@ -51,7 +51,7 @@ inline snrt_dma_txid_t snrt_dma_start_1d_wideptr(uint64_t dst, uint64_t src,
 
         return reg_txid;
     } else {
-        return -1;
+        return 0;
     }
 }
 
@@ -129,7 +129,7 @@ inline snrt_dma_txid_t snrt_dma_start_2d_wideptr(uint64_t dst, uint64_t src,
 
         return reg_txid;
     } else {
-        return -1;
+        return 0;
     }
 }
 
@@ -151,8 +151,7 @@ inline void snrt_dma_wait(snrt_dma_txid_t tid) {
                (    0b000 << 12) | \
                (      (5) <<  7) | \
                (0b0101011 <<  0)   \n"
-        "sub t0, t0, %0 \n"
-        "blez t0, 1b \n" ::"r"(tid)
+        "bltu t0, %0, 1b \n" ::"r"(tid)
         : "t0");
 }
 

sw/tests/dma_empty_transfer.c

@@ -0,0 +1,25 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <snrt.h>
+
+// Allocate a buffer in the main memory which we will use to copy data around
+// with the DMA.
+uint32_t buffer[32];
+
+int main() {
+    if (snrt_global_core_idx() != 8) return 0;  // only DMA core
+
+    // Populate source buffer.
+    uint32_t buffer_src[32];
+    for (uint32_t i = 0; i < 32; i++) {
+        buffer_src[i] = i + 1;
+    }
+
+    // Start a DMA transfer of zero size.
+    snrt_dma_txid_t id = snrt_dma_start_1d(buffer, buffer_src, 0);
+    snrt_dma_wait(id);
+
+    // Test is successful if the previous transfer doesn't block.
+}

sw/tests/dma_simple.c

@@ -21,8 +21,8 @@ int main() {
     }
 
     // Copy data to main memory.
-    snrt_dma_start_1d(buffer, buffer_src, sizeof(buffer));
-    snrt_dma_wait_all();
+    snrt_dma_txid_t id = snrt_dma_start_1d(buffer, buffer_src, sizeof(buffer));
+    snrt_dma_wait(id);
 
     // Check that the main memory buffer contains the correct data.
     for (uint32_t i = 0; i < 32; i++) {

target/snitch_cluster/sw/run.yaml

@@ -9,6 +9,7 @@ runs:
     simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x4
   - elf: tests/build/barrier.elf
   - elf: tests/build/data_mover.elf
+  - elf: tests/build/dma_empty_transfer.elf
   - elf: tests/build/dma_simple.elf
   - elf: tests/build/event_unit.elf
   - elf: tests/build/fence_i.elf