Merge pull request #37 from pulp-platform/new_soc_interconnect

CHANGELOG.md

@@ -6,8 +6,18 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## [Unreleased]
 ### Added
+- Completely replaced soc_interconnect with a new parametric version
+- Added AXI Crossbar to soc_interconnect to attach custom IPs
+- Added new pulp_soc parameter to isolate the axi plug CDC fifo in case it is not needed
+- Add register_interface as dependency to simplify integration of custom ip using reggen
+- Properly assert r_opc signal in new interconnect to indicate bus errors
+- Add error checking for illegal access on HWPE ports which only have access to L2 interleaved memory
 ### Changed
+- AXI ID width of cluster plugs are now set to actually required width instead of a hardcoded one
+- TCDM protocol to SRAM specific protocol is moved from interconnect to memory bank module
 ### Removed
+- obsolete axi_node dependency
+- obsolete header files
 ### Fixed
 
 ## [1.4.1] - 2020-10-28

ips_list.yml

@@ -17,10 +17,15 @@
 #  state of DETACHED HEAD. Before committing any additional
 #  work, make sure to checkout a branch.
 #
-
+common_cells:
+  commit: v1.20.0
+  domain: [cluster, soc]
 L2_tcdm_hybrid_interco:
   commit: pulpissimo-v1.0
   domain: [soc]
+cluster_interconnect:
+  commit: v1.1.0
+  domain: [soc]
 adv_dbg_if:
   commit: v0.0.1
   domain: [cluster, soc]
@@ -34,7 +39,7 @@ apb/apb_fll_if:
   commit: pulpissimo-v1.0
   domain: [soc]
 apb/apb_gpio:
-  commit: v0.2.0
+  commit: 0e9f142f2f11278445c953ad011fce1c7ed85b66
   domain: [soc]
 apb/apb_node:
   commit: v0.1.1
@@ -43,11 +48,11 @@ apb_interrupt_cntrl:
   commit: v0.0.1
   domain: [soc]
 axi/axi:
-  commit: v0.7.1
-  domain: [cluster, soc]
-axi/axi_node:
-  commit: v1.1.4
+  commit: v0.24.1
   domain: [cluster, soc]
+# axi/axi_node:
+#   commit: v1.1.4
+#   domain: [cluster, soc]
 axi/axi_slice:
   commit: v1.1.4
   domain: [cluster, soc]
@@ -57,11 +62,8 @@ axi/axi_slice_dc:
 timer_unit:
   commit: v1.0.2
   domain: [cluster, soc]
-common_cells:
-  commit: v1.13.1
-  domain: [cluster, soc]
 fpnew:
-  commit: v0.6.4
+  commit: v0.6.5
   domain: [cluster, soc]
 jtag_pulp:
   commit: v0.1
@@ -115,3 +117,6 @@ hwpe-mac-engine:
 riscv-dbg:
   commit: v0.2
   domain: [soc]
+register_interface:
+  commit: b1bc9c22e0c2a5801107070c022904498dbae34b
+  domain: [soc]

rtl/components/pulp_interfaces.sv

@@ -585,99 +585,6 @@ interface AXI_BUS_ASYNC2
 
          );
 
-endinterface
-
-interface AXI_LITE
-      #(
-      parameter AXI_ADDR_WIDTH = 32,
-      parameter AXI_DATA_WIDTH = 64,
-      parameter AXI_ID_WIDTH   = 6,
-      parameter AXI_USER_WIDTH = 6
-      );
-
-   localparam AXI_STRB_WIDTH = `EVAL_BE_WIDTH(AXI_DATA_WIDTH);
-
-   logic [AXI_ADDR_WIDTH-1:0] aw_addr;
-   logic                      aw_valid;
-   logic                      aw_ready;
-
-   logic [AXI_DATA_WIDTH-1:0] w_data;
-   logic                      w_valid;
-   logic                      w_ready;
-   logic [AXI_STRB_WIDTH-1:0] w_strb;
-
-   logic                [1:0] b_resp;
-   logic                      b_valid;
-   logic                      b_ready;
-
-   logic [AXI_ADDR_WIDTH-1:0] ar_addr;
-   logic                      ar_valid;
-   logic                      ar_ready;
-
-   logic [AXI_DATA_WIDTH-1:0] r_data;
-   logic                [1:0] r_resp;
-   logic                      r_valid;
-   logic                      r_ready;
-
-
-   // Master Side
-   //***************************************
-   modport Master
-      (
-
-         output aw_addr,
-         output aw_valid,
-         input  aw_ready,
-
-         output w_data,
-         output w_valid,
-         input  w_ready,
-         output w_strb,
-
-         input  b_resp,
-         input  b_valid,
-         output b_ready,
-
-         output ar_addr,
-         output ar_valid,
-         input  ar_ready,
-
-         input  r_data,
-         input  r_resp,
-         input  r_valid,
-         output r_ready
-
-      );
-
-   // Slave Side
-   //***************************************
-   modport Slave
-      (
-
-         input  aw_addr,
-         input  aw_valid,
-         output aw_ready,
-
-         input  w_data,
-         input  w_valid,
-         output w_ready,
-         input  w_strb,
-
-         output b_resp,
-         output b_valid,
-         input  b_ready,
-
-         input  ar_addr,
-         input  ar_valid,
-         output ar_ready,
-
-         output r_data,
-         output r_resp,
-         output r_valid,
-         input  r_ready
-
-      );
-
 endinterface
 
    //********************************************************

rtl/fc/fc_subsystem.sv

@@ -9,8 +9,6 @@
 // specific language governing permissions and limitations under the License.
 
 
-`include "soc_bus_defines.sv"
-
 module fc_subsystem #(
     parameter CORE_TYPE           = 0,
     parameter USE_FPU             = 1,

rtl/include/tcdm_macros.svh

@@ -0,0 +1,73 @@
+`ifndef TCDM_EXPLODE_MACROS_SVH
+`define TCDM_EXPLODE_MACROS_SVH
+
+
+  `define TCDM_EXPLODE_ARRAY_DECLARE(signal_prefix, length) \
+logic [length-1:0]                 signal_prefix``_req; \
+logic [length-1:0][31:0]           signal_prefix``_add; \
+logic [length-1:0]                 signal_prefix``_wen; \
+logic [length-1:0][31:0]           signal_prefix``_wdata; \
+logic [length-1:0][3:0]            signal_prefix``_be; \
+logic [length-1:0]                 signal_prefix``_gnt; \
+logic [length-1:0]                 signal_prefix``_r_opc; \
+logic [length-1:0][31:0]           signal_prefix``_r_rdata; \
+logic [length-1:0]                 signal_prefix``_r_valid;
+
+  `define TCDM_EXPLODE_DECLARE(signal_prefix) \
+logic                  signal_prefix``_req; \
+logic [31:0]           signal_prefix``_add; \
+logic                  signal_prefix``_wen; \
+logic [31:0]           signal_prefix``_wdata; \
+logic [3:0]            signal_prefix``_be; \
+logic                  signal_prefix``_gnt; \
+logic                  signal_prefix``_r_opc; \
+logic [31:0]           signal_prefix``_r_rdata; \
+logic                  signal_prefix``_r_valid;
+
+//Connect a TCDM Master Interface to a set of exploded interface signals
+  `define TCDM_SLAVE_EXPLODE(iface, exploded_prefix, postfix) \
+assign iface.req = exploded_prefix``_req postfix; \
+assign iface.add = exploded_prefix``_add postfix; \
+assign iface.wen = exploded_prefix``_wen postfix; \
+assign iface.wdata = exploded_prefix``_wdata postfix; \
+assign iface.be = exploded_prefix``_be postfix; \
+assign exploded_prefix``_gnt postfix = iface.gnt; \
+assign exploded_prefix``_r_opc postfix = iface.r_opc; \
+assign exploded_prefix``_r_rdata postfix = iface.r_rdata; \
+assign exploded_prefix``_r_valid postfix = iface.r_valid;
+
+//Connect a TCDM Slave Interface to a set of exploded interface signals
+  `define TCDM_MASTER_EXPLODE(iface, exploded_prefix, postfix) \
+assign exploded_prefix``_req postfix = iface.req; \
+assign exploded_prefix``_add postfix = iface.add; \
+assign exploded_prefix``_wen postfix = iface.wen; \
+assign exploded_prefix``_wdata postfix = iface.wdata; \
+assign exploded_prefix``_be postfix = iface.be; \
+assign iface.gnt = exploded_prefix``_gnt postfix; \
+assign iface.r_opc = exploded_prefix``_r_opc postfix; \
+assign iface.r_rdata = exploded_prefix``_r_rdata postfix; \
+assign iface.r_valid = exploded_prefix``_r_valid postfix;
+
+  `define TCDM_ASSIGN_INTF(b, a) \
+assign b.req  = a.req; \
+assign b.add  = a.add; \
+assign b.wen  = a.wen; \
+assign b.wdata  = a.wdata; \
+assign b.be  = a.be; \
+assign a.gnt = b.gnt ; \
+assign a.r_opc = b.r_opc ; \
+assign a.r_rdata= b.r_rdata ; \
+assign a.r_valid = b.r_valid ;
+
+  `define TCDM_ASSIGN(b, postfix_b, a, postfix_a) \
+assign b``_req postfix_b  = a``_req postfix_a; \
+assign b``_add postfix_b  = a``_add postfix_a; \
+assign b``_wen postfix_b  = a``_wen postfix_a; \
+assign b``_wdata postfix_b  = a``_wdata postfix_a; \
+assign b``_be postfix_b  = a``_be postfix_a; \
+assign a``_gnt postfix_a = b``_gnt postfix_b ; \
+assign a``_r_opc postfix_a = b``_r_opc postfix_b ; \
+assign a``_r_rdata postfix_a= b``_r_rdata postfix_b ; \
+assign a``_r_valid postfix_a = b``_r_valid postfix_b ;
+
+`endif