Fix smaller issues and add workaround for synopsys index expression bug

ips_list.yml

@@ -39,7 +39,7 @@ apb/apb_fll_if:
   commit: pulpissimo-v1.0
   domain: [soc]
 apb/apb_gpio:
-  commit: 0e9f142
+  commit: 0e9f142f2f11278445c953ad011fce1c7ed85b66
   domain: [soc]
 apb/apb_node:
   commit: v0.1.1

rtl/pulp_soc/axi64_2_lint32_wrap.sv

@@ -35,12 +35,12 @@ module axi64_2_lint32_wrap
      );
 
     // *Do not change* The legacy wrapper was never tested for other bitwidths.
-    localparam AXI_ADDR_WIDTH  = 32;
-    localparam AXI_DATA_WIDTH  = 64;
-    localparam AXI_STRB_WIDTH  = AXI_DATA_WIDTH/8;
-    localparam TCDM_DATA_WIDTH = 32;
-    localparam TCDM_ADDR_WIDTH = 32;
-    localparam TCDM_BE_WIDTH = TCDM_DATA_WIDTH/8;
+    localparam int unsigned AXI_ADDR_WIDTH  = 32;
+    localparam int unsigned AXI_DATA_WIDTH  = 64;
+    localparam int unsigned AXI_STRB_WIDTH  = AXI_DATA_WIDTH/8;
+    localparam int unsigned TCDM_DATA_WIDTH = 32;
+    localparam int unsigned TCDM_ADDR_WIDTH = 32;
+    localparam int unsigned TCDM_BE_WIDTH = TCDM_DATA_WIDTH/8;
 
     //Explode the output TCDM interface into arrays of individual signals
     `TCDM_EXPLODE_ARRAY_DECLARE(tcdm_slaves, 4)

rtl/pulp_soc/l2_ram_multi_bank.sv

@@ -21,14 +21,14 @@ module l2_ram_multi_bank #(
    XBAR_TCDM_BUS.Slave     mem_pri_slave[2]
 );
     // Don't forget to adjust the SRAM macros and the FPGA settings if you change the banksizes
-    localparam  BANK_SIZE_INTL_SRAM  = 32768; //Number of 32-bit words
-    localparam  BANK_SIZE_PRI0       = 8192; //Number of 32-bit words
-    localparam  BANK_SIZE_PRI1       = 8192; //Number of 32-bit words
+    localparam int unsigned BANK_SIZE_INTL_SRAM  = 32768; //Number of 32-bit words
+    localparam int unsigned BANK_SIZE_PRI0       = 8192; //Number of 32-bit words
+    localparam int unsigned BANK_SIZE_PRI1       = 8192; //Number of 32-bit words
 
     //Derived parameters
-    localparam INTL_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_INTL_SRAM);
-    localparam PRI0_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI0);
-    localparam PRI1_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI1);
+    localparam int unsigned INTL_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_INTL_SRAM);
+    localparam int unsigned PRI0_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI0);
+    localparam int unsigned PRI1_MEM_ADDR_WIDTH = $clog2(BANK_SIZE_PRI1);
 
     //Used in testbenches
 

rtl/pulp_soc/pkg_soc_interconnect.sv

@@ -6,9 +6,12 @@ package pkg_soc_interconnect;
         logic [31:0] end_addr;
     } addr_map_rule_t;
 
-    localparam NR_SOC_TCDM_MASTER_PORTS = 5; // FC instructions, FC data, uDMA RX, uDMA TX, debug access
-    localparam NR_CLUSTER_2_SOC_TCDM_MASTER_PORTS = 4; //  4 ports for 64-bit axi plug
-    localparam NR_TCDM_MASTER_PORTS = NR_SOC_TCDM_MASTER_PORTS + NR_CLUSTER_2_SOC_TCDM_MASTER_PORTS;
-    localparam AXI_ID_OUT_WIDTH = 1 + $clog2(NR_TCDM_MASTER_PORTS);
+    //Warning, if you change the NR_SOC_TCDM_MASTER_PORTS parameter you must also change the identically named preprocessor
+    //macro in soc_interconnect_wrap.sv. The macro is a workaround for a synopsys bug that prevent the usage of parameters
+    //in index expression on the left-hand side of an assignment.
+    localparam int unsigned NR_SOC_TCDM_MASTER_PORTS = 5; // FC instructions, FC data, uDMA RX, uDMA TX, debug access
+    localparam int unsigned NR_CLUSTER_2_SOC_TCDM_MASTER_PORTS = 4; //  4 ports for 64-bit axi plug
+    localparam int unsigned NR_TCDM_MASTER_PORTS = NR_SOC_TCDM_MASTER_PORTS + NR_CLUSTER_2_SOC_TCDM_MASTER_PORTS;
+    localparam int unsigned AXI_ID_OUT_WIDTH = 1 + $clog2(NR_TCDM_MASTER_PORTS);
 
 endpackage : pkg_soc_interconnect

rtl/pulp_soc/soc_interconnect.sv

@@ -160,9 +160,11 @@ module soc_interconnect
 
     //Concatenate the l2 demux master port array and the interleaved only port array
     XBAR_TCDM_BUS interleaved_masters[NR_MASTER_PORTS+NR_MASTER_PORTS_INTERLEAVED_ONLY]();
-    //Synopsys is to stupid to handle expressions for array indices on the left-hand side of assignments. This is a
-    // verbose workaround for it. The next couple of ugly macro magic unpacks each interface into individual signal arrays,
-    // performs the assignments to the interface and packs the signal back to an array of interfaces.
+
+    //Synopsys 2019.3 has a bug; It doesn't handle expressions for array indices on the left-hand side of assignments.
+    // E.g. assign a[param+i] = b[i] doesn't work, but assign a[i] = b[i-param] does.
+    // This is a verbose workaround for it. The next couple of ugly macro magic unpacks each interface into individual
+    // signal arrays, performs the assignments to the interface and packs the signal back to an array of interfaces.
     `TCDM_EXPLODE_ARRAY_DECLARE(interleaved_masters, NR_MASTER_PORTS+NR_MASTER_PORTS_INTERLEAVED_ONLY)
     for (genvar i = 0; i < NR_MASTER_PORTS + NR_MASTER_PORTS_INTERLEAVED_ONLY; i++) begin
         `TCDM_SLAVE_EXPLODE(interleaved_masters[i], interleaved_masters, [i])

rtl/pulp_soc/soc_interconnect_wrap.sv

@@ -138,8 +138,15 @@ module soc_interconnect_wrap
     `TCDM_ASSIGN_INTF(master_ports[2], tcdm_udma_tx)
     `TCDM_ASSIGN_INTF(master_ports[3], tcdm_udma_rx)
     `TCDM_ASSIGN_INTF(master_ports[4], tcdm_debug)
-    for (genvar i = 0; i < pkg_soc_interconnect::NR_CLUSTER_2_SOC_TCDM_MASTER_PORTS; i++) begin
-        `TCDM_ASSIGN_INTF(master_ports[pkg_soc_interconnect::NR_SOC_TCDM_MASTER_PORTS+i], axi_bridge_2_interconnect[i])
+
+    //Assign the 4 master ports from the AXI plug to the interface array
+
+    //Synopsys 2019.3 has a bug; It doesn't handle expressions for array indices on the left-hand side of assignments.
+    // Using a macro instead of a package parameter is an ugly but necessary workaround.
+    // E.g. assign a[param+i] = b[i] doesn't work, but assign a[i] = b[i-param] does.
+    `define NR_SOC_TCDM_MASTER_PORTS 5
+    for (genvar i = 0; i < 4; i++) begin
+        `TCDM_ASSIGN_INTF(master_ports[`NR_SOC_TCDM_MASTER_PORTS + i], axi_bridge_2_interconnect[i])
     end
 
     XBAR_TCDM_BUS contiguous_slaves[3]();

rtl/pulp_soc/tcdm_error_slave.sv

@@ -44,10 +44,10 @@ module tcdm_error_slave #(
         end
     end
 
-`ifndef VERILATOR
+`ifndef SYNTHESIS
     no_req : assert property (
       @(posedge clk_i) disable iff (~rst_ni) not slave.req)
-        else $error("Illegal bus request.");
+        else $error("Illegal bus request to address %x.", slave.add);
 `endif
 
 endmodule : tcdm_error_slave