Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix cheshire_xilinx_top when USE_RESETN is undefined, wire sys_resetn is used but not declared. #172

Open
wants to merge 1 commit into
base: main
Choose a base branch
from

xilinx: Use reset signal corresponding to input polarity in `sys_rst`

9df5811
Select commit
Loading
Failed to load commit list.
Sign in for the full log view
Open

Fix cheshire_xilinx_top when USE_RESETN is undefined, wire sys_resetn is used but not declared. #172

xilinx: Use reset signal corresponding to input polarity in `sys_rst`
9df5811
Select commit
Loading
Failed to load commit list.
GitHub Actions / verible-verilog-lint succeeded Dec 16, 2024 in 0s

reviewdog [verible-verilog-lint] report

reported by reviewdog 🐶

Findings (0)
Filtered Findings (0)
View more details on GitHub Actions