Enable runtime lock for DMR execution.

pulp-platform · Dec 12, 2023 · d9d099f · d9d099f
1 parent 160e22b
commit d9d099f
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Showing 9 changed files with 115 additions and 24 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -92,7 +92,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 70d285ba5b0486b8393dd417e3a7febf80c231fc
+    revision: 6c6265e9e94494eac446f56c999e8c5dce63fbe8
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
@@ -145,7 +145,7 @@ packages:
     - register_interface
     - tech_cells_generic
   redundancy_cells:
-    revision: 936edf25252efc610051b7b944c6506d2f8cfb2b
+    revision: 09cd9514d52145530fa432e6692ed33aec6c04b6
     version: null
     source:
       Git: https://github.com/pulp-platform/redundancy_cells.git

diff --git a/Bender.yml b/Bender.yml
@@ -22,11 +22,11 @@ dependencies:
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.32.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: "70d285b"  } # branch: astral
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: "6c6265e"  } # branch: astral
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.5.1  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
-  redundancy_cells:         { git: "https://github.com/pulp-platform/redundancy_cells.git",       rev: "936edf2" } # branch: astral
+  redundancy_cells:         { git: "https://github.com/pulp-platform/redundancy_cells.git",       rev: "09cd9514" } # branch: astral
   register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.2  }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.0  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }

diff --git a/hw/cva6_wrap.sv b/hw/cva6_wrap.sv
@@ -48,7 +48,7 @@ module cva6_wrap #(
 );
 
 typedef struct packed {
-  cheshire_pkg::doub_bt    bootaddress;
+  // cheshire_pkg::doub_bt    bootaddress;
   cheshire_pkg::doub_bt    hart_id;
   logic  [1:0]             irq;
   logic                    ipi;
@@ -75,10 +75,11 @@ logic                         cores_sync;
 logic          [NumHarts-1:0] core_setback;
 cva6_inputs_t  [NumHarts-1:0] sys2hmr, hmr2core;
 cva6_outputs_t [NumHarts-1:0] hmr2sys, core2hmr;
+cheshire_pkg::doub_bt [NumHarts-1:0] core_bootaddress;
 
 for (genvar i = 0; i < NumHarts; i++) begin: gen_cva6_cores
   // Bind system inputs to HMR.
-  assign sys2hmr[i].bootaddress    = bootaddress_i; // TODO: differentiate?
+  // assign sys2hmr[i].bootaddress    = bootaddress_i; // TODO: differentiate?
   assign sys2hmr[i].hart_id        = hart_id_i + 64'(i);
   assign sys2hmr[i].irq            = irq_i[i];
   assign sys2hmr[i].ipi            = ipi_i[i];
@@ -113,7 +114,8 @@ for (genvar i = 0; i < NumHarts; i++) begin: gen_cva6_cores
     .clk_i            ( clk_i                         ),
     .rst_ni           ( rstn_i                        ),
     .clear_i          ( core_setback[i]               ),
-    .boot_addr_i      ( hmr2core[i].bootaddress       ),
+    // .boot_addr_i      ( hmr2core[i].bootaddress       ),
+    .boot_addr_i      ( core_bootaddress[i]           ),
     .hart_id_i        ( hmr2core[i].hart_id           ),
     .irq_i            ( hmr2core[i].irq               ),
     .ipi_i            ( hmr2core[i].ipi               ),
@@ -186,17 +188,19 @@ if (NumHarts > 1) begin: gen_multicore_hmr
     .rapid_recovery_o ( /* TODO */ ),
     .core_backup_i    (  '0        ), // TODO
 
-    .sys_inputs_i          ( sys2hmr ),
-    .sys_nominal_outputs_o ( hmr2sys ),
-    .sys_bus_outputs_o     (         ),
+    .sys_bootaddress_i     ( bootaddress_i ),
+    .sys_inputs_i          ( sys2hmr       ),
+    .sys_nominal_outputs_o ( hmr2sys       ),
+    .sys_bus_outputs_o     (               ),
     // CVA6 boot does not rely on fetch enable.
-    .sys_fetch_en_i        ( '1      ),
-    .enable_bus_vote_i     ( '0      ), // TODO?
-
-    .core_setback_o         ( core_setback ),
-    .core_inputs_o          ( hmr2core     ),
-    .core_nominal_outputs_i ( core2hmr     ),
-    .core_bus_outputs_i     ( '0           ) // TODO?
+    .sys_fetch_en_i        ( '1            ),
+    .enable_bus_vote_i     ( '0            ), // TODO?
+
+    .core_bootaddress_o     ( core_bootaddress ),
+    .core_setback_o         ( core_setback     ),
+    .core_inputs_o          ( hmr2core         ),
+    .core_nominal_outputs_i ( core2hmr         ),
+    .core_bus_outputs_i     ( '0               ) // TODO?
   );
 
   /* We temporarily hardcode this for permanent lockstep.*/

diff --git a/hw/regs/cheshire_reg_pkg.sv b/hw/regs/cheshire_reg_pkg.sv
@@ -13,6 +13,11 @@ package cheshire_reg_pkg;
   // Typedefs for registers //
   ////////////////////////////
 
+  typedef struct packed {
+    logic [31:0] q;
+    logic        qe;
+  } cheshire_reg2hw_harts_sync_reg_t;
+
   typedef struct packed {
     logic [1:0]  d;
   } cheshire_hw2reg_boot_mode_reg_t;
@@ -87,6 +92,11 @@ package cheshire_reg_pkg;
     } blue_width;
   } cheshire_hw2reg_vga_params_reg_t;
 
+  // Register -> HW type
+  typedef struct packed {
+    cheshire_reg2hw_harts_sync_reg_t harts_sync; // [32:0]
+  } cheshire_reg2hw_t;
+
   // HW -> register type
   typedef struct packed {
     cheshire_hw2reg_boot_mode_reg_t boot_mode; // [166:165]
@@ -122,6 +132,7 @@ package cheshire_reg_pkg;
   parameter logic [BlockAw-1:0] CHESHIRE_HW_FEATURES_OFFSET = 7'h 50;
   parameter logic [BlockAw-1:0] CHESHIRE_LLC_SIZE_OFFSET = 7'h 54;
   parameter logic [BlockAw-1:0] CHESHIRE_VGA_PARAMS_OFFSET = 7'h 58;
+  parameter logic [BlockAw-1:0] CHESHIRE_HARTS_SYNC_OFFSET = 7'h 5c;
 
   // Reset values for hwext registers and their fields
   parameter logic [1:0] CHESHIRE_BOOT_MODE_RESVAL = 2'h 0;
@@ -156,11 +167,12 @@ package cheshire_reg_pkg;
     CHESHIRE_NUM_INT_HARTS,
     CHESHIRE_HW_FEATURES,
     CHESHIRE_LLC_SIZE,
-    CHESHIRE_VGA_PARAMS
+    CHESHIRE_VGA_PARAMS,
+    CHESHIRE_HARTS_SYNC
   } cheshire_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] CHESHIRE_PERMIT [23] = '{
+  parameter logic [3:0] CHESHIRE_PERMIT [24] = '{
     4'b 1111, // index[ 0] CHESHIRE_SCRATCH_0
     4'b 1111, // index[ 1] CHESHIRE_SCRATCH_1
     4'b 1111, // index[ 2] CHESHIRE_SCRATCH_2
@@ -183,7 +195,8 @@ package cheshire_reg_pkg;
     4'b 1111, // index[19] CHESHIRE_NUM_INT_HARTS
     4'b 0011, // index[20] CHESHIRE_HW_FEATURES
     4'b 1111, // index[21] CHESHIRE_LLC_SIZE
-    4'b 0111  // index[22] CHESHIRE_VGA_PARAMS
+    4'b 0111, // index[22] CHESHIRE_VGA_PARAMS
+    4'b 1111  // index[23] CHESHIRE_HARTS_SYNC
   };
 
 endpackage

diff --git a/hw/regs/cheshire_reg_top.sv b/hw/regs/cheshire_reg_top.sv
@@ -17,6 +17,7 @@ module cheshire_reg_top #(
   input  reg_req_t reg_req_i,
   output reg_rsp_t reg_rsp_o,
   // To HW
+  output cheshire_reg_pkg::cheshire_reg2hw_t reg2hw, // Write
   input  cheshire_reg_pkg::cheshire_hw2reg_t hw2reg, // Read
 
 
@@ -157,6 +158,9 @@ module cheshire_reg_top #(
   logic vga_params_green_width_re;
   logic [7:0] vga_params_blue_width_qs;
   logic vga_params_blue_width_re;
+  logic [31:0] harts_sync_qs;
+  logic [31:0] harts_sync_wd;
+  logic harts_sync_we;
 
   // Register instances
 
@@ -917,9 +921,36 @@ module cheshire_reg_top #(
   );
 
 
+  // R[harts_sync]: V(False)
 
+  prim_subreg #(
+    .DW      (32),
+    .SWACCESS("RW"),
+    .RESVAL  (32'h0)
+  ) u_harts_sync (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (harts_sync_we),
+    .wd     (harts_sync_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
 
-  logic [22:0] addr_hit;
+    // to internal hardware
+    .qe     (reg2hw.harts_sync.qe),
+    .q      (reg2hw.harts_sync.q ),
+
+    // to register interface (read)
+    .qs     (harts_sync_qs)
+  );
+
+
+
+
+  logic [23:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == CHESHIRE_SCRATCH_0_OFFSET);
@@ -945,6 +976,7 @@ module cheshire_reg_top #(
     addr_hit[20] = (reg_addr == CHESHIRE_HW_FEATURES_OFFSET);
     addr_hit[21] = (reg_addr == CHESHIRE_LLC_SIZE_OFFSET);
     addr_hit[22] = (reg_addr == CHESHIRE_VGA_PARAMS_OFFSET);
+    addr_hit[23] = (reg_addr == CHESHIRE_HARTS_SYNC_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -974,7 +1006,8 @@ module cheshire_reg_top #(
                (addr_hit[19] & (|(CHESHIRE_PERMIT[19] & ~reg_be))) |
                (addr_hit[20] & (|(CHESHIRE_PERMIT[20] & ~reg_be))) |
                (addr_hit[21] & (|(CHESHIRE_PERMIT[21] & ~reg_be))) |
-               (addr_hit[22] & (|(CHESHIRE_PERMIT[22] & ~reg_be)))));
+               (addr_hit[22] & (|(CHESHIRE_PERMIT[22] & ~reg_be))) |
+               (addr_hit[23] & (|(CHESHIRE_PERMIT[23] & ~reg_be)))));
   end
 
   assign scratch_0_we = addr_hit[0] & reg_we & !reg_error;
@@ -1067,6 +1100,9 @@ module cheshire_reg_top #(
 
   assign vga_params_blue_width_re = addr_hit[22] & reg_re & !reg_error;
 
+  assign harts_sync_we = addr_hit[23] & reg_we & !reg_error;
+  assign harts_sync_wd = reg_wdata[31:0];
+
   // Read data return
   always_comb begin
     reg_rdata_next = '0;
@@ -1177,6 +1213,10 @@ module cheshire_reg_top #(
         reg_rdata_next[23:16] = vga_params_blue_width_qs;
       end
 
+      addr_hit[23]: begin
+        reg_rdata_next[31:0] = harts_sync_qs;
+      end
+
       default: begin
         reg_rdata_next = '1;
       end
@@ -1206,6 +1246,7 @@ module cheshire_reg_top_intf
   input logic rst_ni,
   REG_BUS.in  regbus_slave,
   // To HW
+  output cheshire_reg_pkg::cheshire_reg2hw_t reg2hw, // Write
   input  cheshire_reg_pkg::cheshire_hw2reg_t hw2reg, // Read
   // Config
   input devmode_i // If 1, explicit error return for unmapped register access
@@ -1239,6 +1280,7 @@ module cheshire_reg_top_intf
     .rst_ni,
     .reg_req_i(s_reg_req),
     .reg_rsp_o(s_reg_rsp),
+    .reg2hw, // Write
     .hw2reg, // Read
     .devmode_i
   );

diff --git a/hw/regs/cheshire_regs.hjson b/hw/regs/cheshire_regs.hjson
@@ -131,5 +131,14 @@
       ]
     }
 
+    { name:     "harts_sync"
+      desc:     "Available harts' synchronization request."
+      swaccess: "rw"
+      hwaccess: "hro"
+      hwqe:     "true"
+      fields: [
+        { bits: "31:0", name: "hart_sync", desc: "Harts sync request." }
+      ]
+    }
   ]
 }
diff --git a/sw/include/cheshire_io.h b/sw/include/cheshire_io.h
@@ -9,5 +9,3 @@
 #include "params.h"
 
 void cheshire_init_io();
-
-void cheshire_close_io();
diff --git a/sw/include/regs/cheshire.h b/sw/include/regs/cheshire.h
@@ -123,6 +123,9 @@ extern "C" {
 #define CHESHIRE_VGA_PARAMS_BLUE_WIDTH_FIELD \
   ((bitfield_field32_t) { .mask = CHESHIRE_VGA_PARAMS_BLUE_WIDTH_MASK, .index = CHESHIRE_VGA_PARAMS_BLUE_WIDTH_OFFSET })
 
+// Available harts' synchronization request.
+#define CHESHIRE_HARTS_SYNC_REG_OFFSET 0x5c
+
 #ifdef __cplusplus
 }  // extern "C"
 #endif

diff --git a/sw/include/util.h b/sw/include/util.h
@@ -87,3 +87,25 @@ static inline unsigned int hart_id() {
   asm volatile("csrr %0, mhartid" : "=r" (hart_id) : );
   return hart_id;
 }
+
+// Disable data caches
+static inline void disable_dcache(){
+  asm volatile("csrrwi x0, 0x701, 0x0 \n\t" : : : "memory");
+}
+
+// Enable data caches
+static inline void enable_dcache(){
+  asm volatile("csrrwi x0, 0x701, 0x1 \n\t" : : : "memory");
+}
+
+// Wake up sleeping hart using CLINT
+static inline void wakeup_hart(unsigned int hart_id) {
+  *reg32(&__base_clint, 0x4*hart_id) = 0x1;
+  *reg32(&__base_clint, 0x4*hart_id) = 0x0;
+}
+
+// Write synchronization request in dedicated register
+static inline void sync_req(unsigned int hart_id){
+  uint32_t sync_reg = *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET);
+  *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET) = sync_reg | (0x1 << hart_id);
+}
Original file line number	Diff line number	Diff line change
Expand Up		@@ -9,5 +9,3 @@
		#include "params.h"

		void cheshire_init_io();

		void cheshire_close_io();