xilinx: Changed dram ID width

pulp-platform · Feb 5, 2024 · 82fc244 · 82fc244
1 parent 32854bb
commit 82fc244
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Showing 3 changed files with 4 additions and 4 deletions.
diff --git a/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv b/target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv
@@ -73,7 +73,7 @@ module dram_wrapper_xilinx #(
 `ifdef TARGET_GENESYS2
   localparam dram_cfg_t cfg = '{
     EnCDC         : 1, // 200 MHz axi (attention CDC logdepth)
-    IdWidth       : 4,
+    IdWidth       : 8,
     AddrWidth     : 30,
     DataWidth     : 64,
     StrobeWidth   : 8
@@ -366,4 +366,4 @@ module dram_wrapper_xilinx #(
   );
 `endif  // USE_DDR3
 
-endmodule
+endmodule
diff --git a/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/mig_genesys2.prj
@@ -149,7 +149,7 @@
             <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
             <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
             <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
-            <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
+            <C0_S_AXI_ID_WIDTH>8</C0_S_AXI_ID_WIDTH>
             <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
         </AXIParameters>
     </Controller>

diff --git a/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk b/target/xilinx/xilinx_ips/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.mk
@@ -3,6 +3,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 ROOT_xlnx_mig_7_ddr3               := $(CHS_XIL_DIR)/xilinx_ips/xlnx_mig_7_ddr3 
-ARTIFACTS_FILES_xlnx_mig_7_ddr3    := xlnx_mig_7_ddr3.mk tcl/run.tcl
+ARTIFACTS_FILES_xlnx_mig_7_ddr3    := xlnx_mig_7_ddr3.mk tcl/run.tcl mig_genesys2.prj mig_kc705.prj mig_vc707.prj
 ARTIFACTS_VARS_xlnx_mig_7_ddr3     := xilinx_part XILINX_BOARD xilinx_board_long
 XILINX_USE_ARTIFACTS_xlnx_mig_7_ddr3  := 1