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xilinx: Finishing vanilla makefile flow
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| Original file line number | Diff line number | Diff line change |
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@@ -53,7 +53,7 @@ chs-clean-deps: | |
| ###################### | ||
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| CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git | ||
| CHS_NONFREE_COMMIT ?= d31389c3b559e48496b7264a55ae33eda994bded | ||
| CHS_NONFREE_COMMIT ?= bb52c7ddb3f23e394054e340fdfae3929ebbb60c | ||
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| chs-nonfree-init: | ||
| git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -3,46 +3,34 @@ | |
| # SPDX-License-Identifier: SHL-0.51 | ||
| # | ||
| # Cyril Koenig <[email protected]> | ||
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| source ../scripts/add_sources_vsim.tcl | ||
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| source add_sources_vsim.tcl | ||
| if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} { | ||
| source ips/xlnx_clk_wiz/questa/compile.do | ||
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| if {[string first "xlnx_vio" $::env(IPS)] != -1} { | ||
| source ips/xlnx_vio/questa/compile.do | ||
| }} | ||
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| if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} { | ||
| source ips/xlnx_mig_7_ddr3_ex/questa/compile.do | ||
| source ips/xlnx_mig_7_ddr3/questa/compile.do | ||
| vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v" | ||
| vlog -work work ips/xlnx_mig_7_ddr3_ex/imports/sim_tb_top.v -L xil_defaultlib | ||
| } | ||
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| if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} { | ||
| source ips/xlnx_mig_ddr4_ex/questa/compile.do | ||
| source ips/xlnx_mig_ddr4/questa/compile.do | ||
| vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv" | ||
| vlog -work work ips/xlnx_mig_ddr4_ex/imports/sim_tb_top.sv -L xil_defaultlib | ||
| } | ||
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| # Note : this testbench does not implenent the ddr4 memory model | ||
| ## Note : this testbench does not implenent the ddr4 memory model | ||
| set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl" | ||
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| set XLIB_ARGS "-L secureip -L xpm -L unisims_ver -L unimacro_ver -L work -L xil_defaultlib" | ||
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| if {![info exists VOPTARGS]} { | ||
| set VOPTARGS "+acc" | ||
| } | ||
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| set flags "-permissive -suppress 3009 -suppress 8386 -error 7" | ||
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| set pargs "" | ||
| if {[info exists BOOTMODE]} { append pargs "+BOOTMODE=${BOOTMODE} " } | ||
| if {[info exists PRELMODE]} { append pargs "+PRELMODE=${PRELMODE} " } | ||
| if {[info exists BINARY]} { append pargs "+BINARY=${BINARY} " } | ||
| if {[info exists IMAGE]} { append pargs "+IMAGE=${IMAGE} " } | ||
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| eval "vsim ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${XLIB_ARGS} ${pargs} ${flags} | ||
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| set StdArithNoWarnings 1 | ||
| set NumericStdNoWarnings 1 | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,107 @@ | ||
| 437,438c437,463 | ||
| < example_top # | ||
| < ( | ||
| --- | ||
| > wire cpu_reset; | ||
| > wire cpu_resetn; | ||
| > `ifdef TARGET_XLNX_MIG_DDR4 | ||
| > wire sys_clk_p; | ||
| > wire sys_clk_n; | ||
| > `endif | ||
| > wire testmode_i; | ||
| > wire [1:0] boot_mode_i; | ||
| > wire jtag_tck_i; | ||
| > wire jtag_tms_i; | ||
| > wire jtag_tdi_i; | ||
| > wire jtag_tdo_o; | ||
| > wire jtag_trst_ni; | ||
| > wire jtag_vdd_o; | ||
| > wire jtag_gnd_o; | ||
| > wire uart_tx_o; | ||
| > wire uart_rx_i; | ||
| > | ||
| > assign cpu_reset = sys_rst; | ||
| > assign cpu_resetn = ~cpu_reset; | ||
| > assign boot_mode_i = '0; | ||
| > assign testmode_i = '0; | ||
| > assign jtag_tck_i = '0; | ||
| > assign jtag_tms_i = '0; | ||
| > assign jtag_tdi_i = '0; | ||
| > assign jtag_trst_ni = '0; | ||
| > assign uart_rx_i = '0; | ||
| 440,443c465,468 | ||
| < .SIMULATION (SIMULATION), | ||
| < .BEGIN_ADDRESS (BEGIN_ADDRESS), | ||
| < .END_ADDRESS (END_ADDRESS), | ||
| < .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS), | ||
| --- | ||
| > `ifdef TARGET_XLNX_MIG_DDR4 | ||
| > assign sys_clk_p = c0_sys_clk_p; | ||
| > assign sys_clk_n = c0_sys_clk_n; | ||
| > `endif | ||
| 445,457d469 | ||
| < .COL_WIDTH (COL_WIDTH), | ||
| < .CS_WIDTH (CS_WIDTH), | ||
| < .DM_WIDTH (DM_WIDTH), | ||
| < | ||
| < .DQ_WIDTH (DQ_WIDTH), | ||
| < .DQS_CNT_WIDTH (DQS_CNT_WIDTH), | ||
| < .DRAM_WIDTH (DRAM_WIDTH), | ||
| < .ECC_TEST (ECC_TEST), | ||
| < .RANKS (RANKS), | ||
| < .ROW_WIDTH (ROW_WIDTH), | ||
| < .ADDR_WIDTH (ADDR_WIDTH), | ||
| < .BURST_MODE (BURST_MODE), | ||
| < .TCQ (TCQ), | ||
| 459,473c471,472 | ||
| < | ||
| < .DRAM_TYPE (DRAM_TYPE), | ||
| < | ||
| < | ||
| < .nCK_PER_CLK (nCK_PER_CLK), | ||
| < | ||
| < | ||
| < .C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH), | ||
| < .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH), | ||
| < .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH), | ||
| < .C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST), | ||
| < | ||
| < .DEBUG_PORT (DEBUG_PORT), | ||
| < | ||
| < .RST_ACT_LOW (RST_ACT_LOW) | ||
| --- | ||
| > cheshire_top_xilinx # | ||
| > ( | ||
| 475c474 | ||
| < u_ip_top | ||
| --- | ||
| > u_cheshire_top_xilinx | ||
| 477,502c476 | ||
| < | ||
| < .ddr3_dq (ddr3_dq_fpga), | ||
| < .ddr3_dqs_n (ddr3_dqs_n_fpga), | ||
| < .ddr3_dqs_p (ddr3_dqs_p_fpga), | ||
| < | ||
| < .ddr3_addr (ddr3_addr_fpga), | ||
| < .ddr3_ba (ddr3_ba_fpga), | ||
| < .ddr3_ras_n (ddr3_ras_n_fpga), | ||
| < .ddr3_cas_n (ddr3_cas_n_fpga), | ||
| < .ddr3_we_n (ddr3_we_n_fpga), | ||
| < .ddr3_reset_n (ddr3_reset_n), | ||
| < .ddr3_ck_p (ddr3_ck_p_fpga), | ||
| < .ddr3_ck_n (ddr3_ck_n_fpga), | ||
| < .ddr3_cke (ddr3_cke_fpga), | ||
| < .ddr3_cs_n (ddr3_cs_n_fpga), | ||
| < | ||
| < .ddr3_dm (ddr3_dm_fpga), | ||
| < | ||
| < .ddr3_odt (ddr3_odt_fpga), | ||
| < | ||
| < | ||
| < .sys_clk_i (sys_clk_i), | ||
| < | ||
| < .init_calib_complete (init_calib_complete), | ||
| < .tg_compare_error (tg_compare_error), | ||
| < .sys_rst (sys_rst) | ||
| --- | ||
| > .* |
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