fpga: Add flow and CI for implementation on VCU128 boards

Bender.lock

@@ -233,7 +233,7 @@ packages:
     dependencies:
     - common_cells
   fpu_interco:
-    revision: 0769976fa51bdd820656a01161a4c46b88c59ac5
+    revision: c985d54c2b078ddfbec8c2a498f453410bbdc93e
     version: null
     source:
       Git: https://github.com/pulp-platform/fpu_interco.git
@@ -371,7 +371,7 @@ packages:
     dependencies:
     - axi_slice
   pulp_cluster:
-    revision: a746000f9dc9965e1351186905b59bca36edef57
+    revision: 314f9a04f8dad4a5eeb0b9e8ad84898c6dc3f81e
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp_cluster.git
@@ -433,7 +433,7 @@ packages:
     - common_cells
     - common_verification
   riscv:
-    revision: 4eac53237c6d0062715d17016fe95462eb81ebc3
+    revision: 6187537f9994d16bad2d721c0f5ebc5193c0f010
     version: null
     source:
       Git: [email protected]:AlSaqr-platform/riscv_nn.git

Bender.yml

@@ -16,7 +16,7 @@ dependencies:
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: 2adb7271438cdb96c19fbaf3e2a6bf89ffeee568 } # branch: lv/phys_in_use
   car_l2:             { git: [email protected]:carfield/carfield_l2_mem.git,       rev: 4239b2a510d65aa110bcc8a070e434cabd1a8b9a } # branch: main
   safety_island:      { git: [email protected]:carfield/safety-island.git,         rev: 60e768a3ef29f47339e31674d497293f5a768893 } # branch: atops
-  pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: a746000f9dc9965e1351186905b59bca36edef57 } # branch: yt/carfield-integration
+  pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: 314f9a04f8dad4a5eeb0b9e8ad84898c6dc3f81e } # branch: yt/carfield-integration
   opentitan:          { git: https://github.com/alsaqr-platform/opentitan.git,          rev: 5ce64a6225e971c1e00ece29aa485f23a31aa7b2 } # branch: carfield
   mailbox_unit:       { git: [email protected]:pulp-platform/mailbox_unit.git,             version: 1.1.0                                }
   apb:                { git: https://github.com/pulp-platform/apb.git,                  version: 0.2.3                                }
@@ -27,6 +27,7 @@ dependencies:
   bus_err_unit:       { git: [email protected]:carfield/bus_err_unit.git,          rev: 47a6436dc4b4b7f4a44f7786033b22c6d01530b2 } # branch: main
   common_cells:       { git: https://github.com/pulp-platform/common_cells.git,         version: 1.30.0                               }
 
+
 workspace:
   package_links:
     cheshire: cheshire
@@ -58,9 +59,15 @@ sources:
     files:
       - scripts/spyglass/src/carfield_wrap.sv
 
-  - target: synthesis
+  - target: all(synthesis, not(fpga))
     files:
       - target/synth/carfield_synth_wrap.sv
+
+  - target: all(xilinx, fpga)
+    files:
+      - target/xilinx/src/carfield_top_xilinx.sv
+      - target/xilinx/src/dram_wrapper.sv
+      - target/xilinx/src/overrides/tc_clk_xilinx.sv
 
   - target: intel16_elab_only
     files:

bender-xilinx.mk

@@ -0,0 +1,25 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Cyril Koenig <[email protected]>
+
+# bender targets
+xilinx_targs += -t fpga
+
+# bender defines
+xilinx_defs += -D PULP_FPGA_EMUL
+
+# Conditionally add GEN_{island} to bender define
+define check_enable_island
+ifeq ($($(1)),1)
+xilinx_defs += -D$(1)=1
+endif
+endef
+
+$(eval $(call check_enable_island,GEN_PULP_CLUSTER))
+$(eval $(call check_enable_island,GEN_SAFETY_ISLAND))
+$(eval $(call check_enable_island,GEN_SPATZ_CLUSTER))
+$(eval $(call check_enable_island,GEN_OPEN_TITAN))
+
+# note : bender targets are later modified in xilinx.mk

carfield.mk

@@ -9,10 +9,12 @@
 CAR_ROOT ?= .
 CHS_ROOT ?= $(CAR_ROOT)/cheshire
 CAR_SW_DIR := $(CAR_ROOT)/sw
+CAR_XIL_DIR := $(CAR_ROOT)/target/xilinx
 
 # Bender
 BENDER   ?= bender
 QUESTA   ?= questa-2022.3
+VIVADO   ?= vitis-2020.2 vivado
 TBENCH   ?= tb_carfield_soc
 BOOTMODE ?= 0 # default passive bootmode
 PRELMODE ?= 1 # default serial link preload
@@ -43,6 +45,7 @@ CHS_IMAGE    ?=
 # (the following includes are mandatory)
 include $(CAR_ROOT)/bender-common.mk
 include $(CAR_ROOT)/bender-synth.mk
+include $(CAR_ROOT)/bender-xilinx.mk
 
 # Setup Virtual Environment for python scripts (reggen)
 VENVDIR?=$(WORKDIR)/.venv
@@ -72,7 +75,7 @@ endif
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= c75d038822b71a7a52fb24f98d967f0bf1c7f3c6
+CAR_NONFREE_COMMIT ?= 3c2bf51894b699a49eb8e69e21ade567e1b28b49
 
 ## Clone the non-free verification IP for the Carfield TB
 car-nonfree-init:
@@ -238,6 +241,16 @@ SPYGLASS_DEFS += $(synth_defs)
 lint:
 	$(MAKE) -C scripts lint bender_defs="$(SPYGLASS_DEFS)" bender_targs="$(SPYGLASS_TARGS)" > make.log
 
+#############
+# Emulation #
+#############
+
+include $(CAR_XIL_DIR)/xilinx.mk
+
+########
+# Help #
+########
+
 # Setup Autodocumentation of the Makefile
 HELP_TITLE="Carfield Open-Source RTL"
 HELP_DESCRIPTION="Hardware generation and simulation targets for Carfield"

hw/carfield.sv

@@ -21,6 +21,7 @@ module carfield
   import spatz_cluster_pkg::*;
 #(
   parameter cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault,
+  parameter islands_cfg_t IslandsCfg = carfield_pkg::IslandsCfgDefault,
   parameter int unsigned HypNumPhys  = 2,
   parameter int unsigned HypNumChips = 2,
   parameter type reg_req_t           = logic,
@@ -1204,6 +1205,7 @@ assign safed_intrs = {
 };
 // verilog_lint: waive-stop line-length
 
+if (IslandsCfg.EnSafetyIsland) begin : gen_safety_island
 safety_island_synth_wrapper #(
   .SafetyIslandCfg          ( SafetyIslandCfg            ),
   .AxiAddrWidth             ( Cfg.AddrWidth              ),
@@ -1290,6 +1292,10 @@ safety_island_synth_wrapper #(
   .async_axi_out_r_wptr_i  ( axi_mst_ext_r_wptr  [SafetyIslandMstIdx] ),
   .async_axi_out_r_rptr_o  ( axi_mst_ext_r_rptr  [SafetyIslandMstIdx] )
 );
+end
+else begin : gen_no_safety_island
+  assign jtag_safety_island_tdo_o = jtag_safety_island_tdi_i;
+end
 
 // PULP integer cluster
 
@@ -1298,6 +1304,7 @@ assign car_regs_hw2reg.pulp_cluster_eoc.de  = 1'b1;
 assign car_regs_hw2reg.pulp_cluster_busy.de = 1'b1;
 assign car_regs_hw2reg.pulp_cluster_eoc.d = pulpcl_eoc;
 
+if (IslandsCfg.EnPulpCluster) begin : gen_pulp_cluster
 pulp_cluster #(
   .NB_CORES                       ( IntClusterNumCores        ),
   .NB_HWPE_PORTS                  ( IntClusterNumHwpePorts    ),
@@ -1397,6 +1404,7 @@ pulp_cluster #(
   .async_data_master_b_wptr_i  ( axi_mst_intcluster_b_wptr  ),
   .async_data_master_b_rptr_o  ( axi_mst_intcluster_b_rptr  )
 );
+end
 
 // Floating Point Spatz Cluster
 
@@ -1408,6 +1416,7 @@ logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_mbox_intr;
 logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_timer_intr = { chs_mti[FPClusterIntrHart1Idx], chs_mti[FPClusterIntrHart0Idx] };
 // verilog_lint: waive-stop line-length
 
+if (IslandsCfg.EnSpatzCluster) begin : gen_spatz_cluster
 spatz_cluster_wrapper #(
     .AxiAddrWidth             ( Cfg.AddrWidth     ),
     .AxiDataWidth             ( Cfg.AxiDataWidth  ),
@@ -1497,10 +1506,12 @@ spatz_cluster_wrapper #(
    .async_axi_out_r_rptr_o  ( axi_mst_ext_r_rptr  [FPClusterMstIdx] ),
    .cluster_probe_o         ( car_regs_hw2reg.spatz_cluster_busy.d  )
   );
+end
 
 // Security Island
 logic secd_mbox_intr;
 
+if (IslandsCfg.EnOpenTitan) begin : gen_secure_subsystem
 secure_subsystem_synth_wrap #(
   .HartIdOffs            ( OpnTitHartIdOffs           ),
   .AxiAddrWidth          ( Cfg.AddrWidth              ),
@@ -1576,6 +1587,10 @@ secure_subsystem_synth_wrap #(
   .spi_host_SD_i    ( spih_ot_sd_i     ),
   .spi_host_SD_en_o ( spih_ot_sd_en_o  )
 );
+end
+else begin : gen_no_secure_subsystem
+  assign jtag_ot_tdo_o = jtag_ot_tdi_i;
+end
 
 // Security Island Mailbox
 // Host Clock Domain
@@ -1750,6 +1765,7 @@ axi_lite_mailbox_unit #(
 carfield_axi_slv_req_t axi_ethernet_req;
 carfield_axi_slv_rsp_t axi_ethernet_rsp;
 
+if (IslandsCfg.EnEthernet) begin : gen_ethernet
 axi_cdc_dst #(
   .LogDepth   ( LogDepth                   ),
   .aw_chan_t  ( carfield_axi_slv_aw_chan_t ),
@@ -1797,6 +1813,7 @@ axi_err_slv #(
   .slv_req_i  ( axi_ethernet_req       ),
   .slv_resp_o ( axi_ethernet_rsp       )
 );
+end
 
 // APB peripherals
 // Periph Clock Domain
@@ -2174,6 +2191,7 @@ assign reg_bus_hyper.ready = reg_hyper_rsp.ready;
 // CAN bus
 logic [63:0] can_timestamp;
 assign can_timestamp = '1;
+if (IslandsCfg.EnCan) begin : gen_can
 can_top_apb #(
   .rx_buffer_size   ( 32                    ),
   .txt_buffer_count ( 2                     ),
@@ -2198,5 +2216,6 @@ can_top_apb #(
   .s_apb_pwdata     ( apb_mst_req[CanIdx].pwdata  ),
   .s_apb_pwrite     ( apb_mst_req[CanIdx].pwrite  )
 );
+end
 
 endmodule

hw/carfield_pkg.sv

@@ -321,6 +321,27 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
   default: '0
 };
 
+// Control which island to add (for FPGA)
+typedef struct packed {
+  bit     EnPulpCluster;
+  bit     EnSafetyIsland;
+  bit     EnSpatzCluster;
+  bit     EnOpenTitan;
+  bit     EnCan;
+  bit     EnEthernet;
+} islands_cfg_t;
+
+// Enable all islands by default
+localparam islands_cfg_t IslandsCfgDefault = '{
+  EnPulpCluster   : 1,
+  EnSafetyIsland  : 1,
+  EnSpatzCluster  : 1,
+  EnOpenTitan     : 1,
+  EnCan           : 1,
+  EnEthernet      : 1,
+  default         : '1
+};
+
 /*****************/
 /* L2 Parameters */
 /*****************/

target/xilinx/README.md

@@ -0,0 +1,13 @@
+# VCU128 emulation
+
+```bash
+# Build the bitstream:
+make
+# Re-build the bitstream without
+# re-building the IPs:
+make rebuild-top
+# Simulate with the IPs
+# Note you need to generate the
+# Vivado IP models before
+make sim
+```