Put vcs and vsim defines in quotes

CHANGELOG.md

@@ -5,6 +5,8 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
 ## Unreleased
+### Fixed
+- Put `vcs`, `vsim`, and `riviera` defines in quotes.
 
 ## 0.28.1 - 2024-02-22
 ### Added

src/script_fmt/riviera_tcl.tera

@@ -3,7 +3,7 @@ set ROOT "{{ root }}"
 vlib work
 {% if compilation_mode == 'separate' %}{% for group in srcs %}{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}vlog -sv \
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
-    {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
     {% endfor %}{% elif group.file_type == 'vhdl' %}vcom -2008 \
     {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
@@ -13,7 +13,7 @@ vlib work
 
 {% endfor %}{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
-    {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for define in all_defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
     {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
     {% else %}\

src/script_fmt/vcs_sh.tera

@@ -5,7 +5,7 @@ ROOT="{{ root }}"
 {% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \
     -full64 \
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
-    {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
     {% endfor %}{% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \
     {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
@@ -15,7 +15,7 @@ ROOT="{{ root }}"
 {% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{{ vlogan_bin }} -sverilog \
     -full64 \
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
-    {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for define in all_defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
     {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
     {% endif %}{% if loop.last %}

src/script_fmt/vsim_tcl.tera

@@ -6,7 +6,7 @@ set ROOT "{{ root }}"
 #}{% if group.file_type == 'verilog' %}vlog -incr -sv \{#                                                       Compile verilog (& systemverilog) files with vlog -sv #}
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
     {% endfor %}{#                                                                                              Add all vlog arguments
-#}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+#}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{#                                                                                              Add group's defines
 #}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
     {% endfor %}{#                                                                                              Add group's include directories
@@ -25,7 +25,7 @@ set ROOT "{{ root }}"
 #}vlog -incr -sv \{#                                                                                            Compile verilog (& systemverilog) files with vlog -sv #}
     {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
     {% endfor %}{#                                                                                              Add all vlog arguments
-#}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+#}{% for define in all_defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \
     {% endfor %}{#                                                                                              Add all defines
 #}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
     {% endfor %}{#                                                                                              Add all include directories