v0.18.1

Changes since 0.18.0

Fixed

• axi_modify_address: Fix unconnected w_valid.
• axi_dw_converter: Fix internal inversion of up- and downconversion, which led to incorrect lane
  steering and serialization.
• rand_axi_master (in axi_test): In ATOP mode, this module could get stuck receiving an R beat
  when only writes (without ATOP read responses) were left to complete. This has been fixed.
• assign.svh: Remove spurious semicolons.
• axi_lite_to_apb: Fix message of assertion checking the strobe width.

v0.18.0

Changes since 0.17.0

Added

• axi_dw_converter: a data width converter between AXI interfaces of any data width. Depending on
  its parametrization, this module instantiates one of the following:
  • axi_dw_downsizer: a data width converter between a wide AXI master and a narrower slave.
  • axi_dw_upsizer: a data width converter between a narrow AXI master and a wider slave.

v0.17.0

Changes since 0.16.3

Added

• Add axi_isolate to isolate downstream slaves from receiving new transactions.

Changed

• axi_lite_to_axi: Add mandatory AxiDataWidth parameter to enable fix mentioned below.

Fixed

• Improve compatibility with Xcelium:
  • by removing unsupported hierarchical argument to $bits() function in axi_lite_to_axi;
  • by removing unsupported struct assignment in axi_lite_demux.

v0.16.3

Changes since 0.16.2

Changed

• axi_err_slv: Add optional parameter to define data returned by read response. The parameter
  defaults to a 64-bit value, so buses with data width larger than or equal to 64 bit see an
  additional 32-bit value in error responses compared to the prior version. Other than that, this
  change is fully backward compatible.

v0.16.2

Changes since 0.16.1

Fixed

• axi_atop_filter: Fix underflow in counter for AxiMaxWriteTxns = 1.

v0.16.1

Changes since 0.16.0

Fixed

• Remove whitespace in and semicolon after macro calls.
• axi_intf: Improve Verilator compatibility by disabling unsupported assertions.

v0.16.0

Changes since 0.15.1

Added

• axi_cdc_intf: Add interface variant of AXI clock domain crossing.

Fixed

• axi_cdc: Remove unused global import axi_pkg::*.
• axi_intf: Remove global import axi_pkg::* and explicitly use symbols from axi_pkg.
• axi_lite_cut_intf: Add missing assigns to and from interface ports.
• tb_axi_cdc:
  • Remove global import axi_pkg::*.
  • Define channels with AXI_TYPEDEF macros instead of local typedefs.

Removed

• Remove unused AXI_ARBITRATION and AXI_ROUTING_RULES interfaces.

v0.15.1

Changes since 0.15.0

Added

• axi_intf: Add single-channel assertions to AXI_BUS_DV.

Fixed

• axi_lite_to_apb: Fix the interface version (axi_lite_to_apb_intf) to match the changes from
  version 0.15.0.
• axi_demux: When MaxTrans was 1, the IdCounterWidth became 0. This has been fixed.
• axi_atop_filter:
  • The master interface of this module in one case depended on aw_ready before applying
    w_valid, which is a violation of the AXI specification that can lead to deadlocks. This issue
    has been fixed by removing that dependency.
  • The slave interface of this module could illegally change the value of B and R beats between
    valid and handshake. This has been fixed.
• rand_axi_master (in axi_test):
  • Fix infinite wait in send_ws task.
  • Decouple generation of AWs from sending them. This allows to apply W beats before or
    simultaneous with AW beats.
• rand_axi_slave (in axi_test):
  • Decouple receiving of Ws from receiving of AWs. This allows to receive W beats independent of
    AW beats.
• Update common_cells to 1.16.4 to fix synthesis warning in id_queue.

v0.15.0

Changes since 0.14.0

Added

• axi_burst_splitter: Split AXI4 bursts to single-beat transactions.

Changed

• axi_lite_to_apb: The psel field of the apb_req_t struct is now a single bit. That is, every
  APB slave has its own request struct. Accordingly, apb_req_o is now an array with NoApbSlaves
  entries.
• axi_decerr_slv has been replaced by a more generic axi_err_slv, which takes the kind of error
  as parameter. This axi_err_slv no longer has a FallThrough parameter; instead, a response
  (i.e., B or R beat) now always comes one cycle after the AW or AR beat (as required by the AXI
  Spec) but the slave can accept a W beat in the same cycle as the corresponding AW beat.
  Additionally, axi_err_slv got a parameter ATOPs that defines if it supports atomic operations.
• axi_to_axi_lite: Rework module to structs and add burst support.

Fixed

• axi_demux: The case statement controlling the counters had not been specified unique even
  though it qualified for it. This has been fixed.
• axi_lite_mux_intf: Fix signal names in internal assignments, names of parameters of
  axi_lite_mux instance, and typos in assertion messages.

v0.14.0

Changes since 0.13.0

Added

• Add axi_lite_mailbox: AXI4-Lite mailbox.