Releases: pulp-platform/axi
Releases · pulp-platform/axi
v0.30.0
Added
- Add
axi_lite_xbar_intf
interface variant ofaxi_lite_xbar
.
Fixed
axi_lite_demux
: Improve compatibility with new version of QuestaSim's optimizer (vopt
).
Before this workaround, QuestaSim 2021.1 could segfault on instances ofaxi_lite_demux
.
v0.29.2
Fixed
axi_demux
: Improve compatibility with VCS (#187). The workaround of #169 was not compatible
with VCS 2020.12. That workaround is now only active ifTARGET_VSIM
is defined.axi_dw_downsizer
andaxi_dw_upsizer
(part ofaxi_dw_converter
): Avoid latch inference on the
Mentor Precision synthesis tool.axi_lite_cdc_src_intf
: Fix_i
and_o
suffixes in instantiation ofaxi_cdc_src
.axi_test::axi_rand_slave
: Improve compatibility with VCS (#175).axi_test::axi_scoreboard
: Add default value to parameters to improve compatibility with some
tools.
v0.29.1
Fixed
axi_lite_to_apb_intf
: Add missing parameters, which were added toaxi_lite_to_apb
in v0.28.0.
v0.29.0
Changed
axi_xbar
andaxi_demux
: Add support for unique IDs by adding aUniqueIds
parameter to both
modules (#172). If you can guarantee that the ID of each transaction is always unique among all
in-flight transactions in the same direction, setting theUniqueIds
parameter to1'b1
simplifies the demultiplexer (see documentation ofaxi_demux
for details). This change is
backward-compatible onaxi_demux
(because the default value of the new parameter is1'b0
).
Asaxi_xbar
is configured with thexbar_cfg_t
struct
, this change is not
backward-compatible foraxi_xbar
(except forxbar_cfg_t
s initialized with adefault
part).
Fixed
axi_test::axi_rand_master
: Refactor ID legalization into common function to simplify the
implementation and remove redundant code. No known functional bug was fixed, but the correctness
of the refactored code can be asserted more easily.
v0.28.0
Added
- Add source- and destination-clock-domain "halves" for the clock domain crossing (CDC):
axi_cdc_src
andaxi_cdc_dst
. This is implemented by refactoring theaxi_cdc
module, so the
implementation is reused from the existingaxi_cdc
module. To avoid code duplication,axi_cdc
now instantiates anaxi_cdc_src
connected to anaxi_cdc_dst
.
Changed
axi_lite_to_apb
: Make pipeline registers on request and response path optional (can be enabled
with the newPipelineRequest
andPipelineResponse
parameter
s), and disable those pipeline
registers by default.
Fixed
axi_demux
: Improve compatibility with new version of QuestaSim's optimizer (vopt
) (#169).
Before this workaround, QuestaSim 2020.2 and 2021.1 could segfault on instances ofaxi_demux
.
v0.27.1
Fixed
axi_dw_downsizer
andaxi_dw_upsizer
(part ofaxi_dw_converter
): Fix declaration order of
w_req_t
,w_req_d
, andw_req_q
to remove problematic forward references.- FuseSoC: Fix version of
common_cells
(1.21.0
).
v0.27.0
Added
assign.svh
: Add macros for assigning between AXI-Litestruct
s, both inside a process
(AXI_LITE_SET_*_STRUCT
) and outside a process (AXI_LITE_ASSIGN_*_STRUCT
). This is safer than
assigningstruct
s with a simple=
, because the macros assign individual fields.typedef.svh
: AddAXI_TYPEDEF_ALL
andAXI_LITE_TYPEDEF_ALL
macros for defining all channels
and request/responsestruct
s of an AXI4+ATOPs and an AXI4-Lite interface, respectively, in a
single macro call.axi_test::axi_rand_slave
: Add parameterRAND_RESP
, which enables randomization of theresp
field in B and R beats.
Changed
axi_test::axi_rand_master
: Randomize the QoS field.- Update
common_verification
dependency to0.2.0
, which has been released for more than a year. - Update
common_cells
dependency to1.21.0
to align on version0.2.0
of the
common_verification
dependency. This includes version1.20.1
ofcommon_cells
, which fixes
an out-of-bounds index inaxi_burst_splitter
(#150).
v0.26.0
Added
- Add infinite, simulation-only memory
axi_sim_mem
. assign.svh
: Add macros for assigning betweenstruct
s, both inside a process
(AXI_SET_*_STRUCT
) and outside a process (AXI_ASSIGN_*_STRUCT
). This is safer than assigning
struct
s with a simple=
, because the macros assign individual fields. (Fields that mismatch
between twostruct
s, e.g., due to differentuser
signal widths, should, and in some cases
must, be still assigned separately.)
Changed
- Rename the following classes in
axi_test
to follow the convention that all user-facing objects
in this repository start withaxi_
:rand_axi_lite_master
toaxi_lite_rand_master
,rand_axi_lite_slave
toaxi_lite_rand_slave
,rand_axi_master
toaxi_rand_master
, andrand_axi_slave
toaxi_rand_slave
.
v0.25.0
Added
axi_xbar
: Add parameter to disable support for atomic operations (ATOPs
).
Changed
AXI_BUS
,AXI_BUS_ASYNC
,AXI_BUS_DV
,AXI_LITE
, andAXI_LITE_DV
: Change type of every
parameter fromint
toint unsigned
. An unsigned type is more appropriate, because none of
those parameters can actually take a negative value, and it improves compatibility with some
tools.axi_test::rand_axi_lite_slave
andaxi_test::rand_axi_lite_master
: Change type of address and
data width parameters (AW
andDW
) fromint
toint unsigned
. Same rationale as for
AXI_BUS
(et al.) above.
Fixed
axi_demux
: Break combinatorial simulation loop.axi_xbar
: Improve compatibility with vsim version 10.6c (and earlier) by introducing a
workaround for a tool limitation (#133).tb_axi_lite_regs
: Removed superfluous hardcoded assertion.- Improve compatibility with Vivado XSim by disabling formal properties in
axi_demux
,
axi_err_slv
, andaxi_xbar
ifXSIM
is defined.
v0.24.2
Changed
axi_test::rand_axi_lite_master
andaxi_test::rand_axi_lite_slave
: Specify default values for
parameters to improve compatibility with tools that require a default value for every parameter.
Fixed
axi_lite_demux
: Movetypedef
out ofgenerate
block to improve compatibility with VCS.axi_test::rand_axi_master
andaxi_test::rand_axi_slave
: Fix call torandomize
function for
class variables. Prior to this fix, thestd::randomize()
function was used for three class
variables, but class variables must use the.randomize()
member function.