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[HW] Refactor the MASKU #376

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merged 8 commits into from
Dec 8, 2024
Merged

[HW] Refactor the MASKU #376

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55fded5
[hardware] Simplify the operand queues
mp-17 Nov 9, 2024
a570818
[hardware] Slim down addrgen check function
mp-17 Nov 9, 2024
66c4f34
[hardware] Replace stream regs with spill regs
mp-17 Nov 9, 2024
5995d45
[hardware] Fix some latches
mp-17 Nov 25, 2024
b04759d
[apps] Improve MASKU riscv-tests
mp-17 Nov 9, 2024
7015639
[hardware] Refactor the MASKU
mp-17 Nov 9, 2024
215edf7
[hardware] :bug: Fix legality check in dispatcher
mp-17 Nov 15, 2024
634a753
[CHANGELOG] Update Changelog
mp-17 Nov 25, 2024
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6 changes: 6 additions & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Bump upload and delete artifact actions
- Fix synthesis-unfriendly constructs
- Fix vector slicing bug in operand requesters
- Fix legality check for allowed registers in dispatcher
- Remove a couple of latches

### Added

Expand All @@ -39,6 +41,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Add multi-precision conv3d
- Add support for unit-stride, non-unit-stride, indexed segment memory instructions
- Add support for fault-only-first loads
- Extend the riscv-tests MASKU-related tests

### Changed

Expand Down Expand Up @@ -69,6 +72,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Refactor MASKU
- Remove bit-support for tail elements
- Adapt mask tests to this behavior
- Refactor the MASKU
- The MASKU always receives balanced payloads from the lanes
- Remove FPU support for opqueues that do not need it

## 3.0.0 - 2023-09-08

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2 changes: 1 addition & 1 deletion apps/riscv-tests/isa/macros/vector/dataset.h
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Expand Up @@ -7,7 +7,7 @@
#ifndef __DATASET_H__
#define __DATASET_H__

#define SIZE 64
#define SIZE 1024
#define L_SIZE 1024

static volatile uint64_t Au64[SIZE] __attribute__((aligned(128)));
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11 changes: 11 additions & 0 deletions apps/riscv-tests/isa/macros/vector/vector_macros.h
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Expand Up @@ -209,6 +209,17 @@ int test_case;
asm volatile("vsetvl zero, %[vl], %[vtype]" :: [vl] "r" (vl), [vtype] "r" (vtype)); \
} while(0)

#define VCLEAR_AT_ONE(register) \
do { \
MEMORY_BARRIER; \
uint64_t vtype; uint64_t vl; uint64_t vlmax; \
asm volatile("csrr %[vtype], vtype" : [vtype] "=r" (vtype)); \
asm volatile("csrr %[vl], vl" : [vl] "=r" (vl)); \
asm volatile("vsetvl %[vlmax], zero, %[vtype]" : [vlmax] "=r" (vlmax) : [vtype] "r" (vtype)); \
asm volatile("vmv.v.i "#register", -1"); \
asm volatile("vsetvl zero, %[vl], %[vtype]" :: [vl] "r" (vl), [vtype] "r" (vtype)); \
} while(0)

// Macro to initialize a vector with progressive values from a counter
#define INIT_MEM_CNT(vec_name, size) \
counter = 0; \
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86 changes: 76 additions & 10 deletions apps/riscv-tests/isa/rv64uv/vcpop.c
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Expand Up @@ -15,24 +15,90 @@ void TEST_CASE1(void) {
VLOAD_32(v0, 5, 0, 0, 0);
volatile uint32_t scalar = 1337;
volatile uint32_t OUP[] = {0, 0, 0, 0};
__asm__ volatile("vpopc.m %[A], v2, v0.t \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
asm volatile("vpopc.m %[A], v2, v0.t \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(1, OUP[0], 2);

VSET(32, e32, m1);
VLOAD_32(v8, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF,
0x88, 0x1, 0x1F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
VLOAD_32(v0, 0xffffffffffffffff, 0xfffffffffffffff7, 0xffffffffffffffff,
0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
0xefffffffffffffff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
VSET(1024, e8, m8);
asm volatile("vpopc.m %[A], v8, v0.t \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(2, OUP[0], 159);
}

// unmasked
void TEST_CASE2(void) {
VSET(4, e32, m1);
VLOAD_32(v2, 0xF, 0, 0, 0);
VLOAD_32(v2, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F);
volatile uint32_t scalar = 1337;
volatile uint32_t OUP[] = {0, 0, 0, 0};
__asm__ volatile("vpopc.m %[A], v2 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(2, OUP[0], 4);
VSET(128, e32, m2);
asm volatile("vpopc.m %[A], v2 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(3, OUP[0], 40);

VSET(8, e32, m1);
VLOAD_32(v0, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
0x1, 0x1F);
VSET(256, e8, m8);
asm volatile("vpopc.m %[A], v0 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(4, OUP[0], 80);

VSET(16, e32, m1);
VLOAD_32(v0, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF,
0x88, 0x1, 0x1F);
VSET(1024, e8, m8);
asm volatile("vpopc.m %[A], v0 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(5, OUP[0], 160);

VSET(8, e32, m1);
VLOAD_32(v2, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
0x1, 0x1F);
VSET(256, e8, m1);
asm volatile("vpopc.m %[A], v2 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(6, OUP[0], 80);

VSET(2, e32, m1);
VLOAD_8(v2, 0xFF, 0x88);
VSET(16, e16, m1);
asm volatile("vcpop.m %[A], v2 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(7, OUP[0], 10);

VSET(4, e32, m1);
VLOAD_32(v2, 0xF, 0, 0, 0);
asm volatile("vpopc.m %[A], v2 \n"
"sw %[A], (%1) \n"
:
: [A] "r"(scalar), "r"(OUP));
XCMP(8, OUP[0], 4);
}

int main(void) {
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13 changes: 12 additions & 1 deletion apps/riscv-tests/isa/rv64uv/vid.c
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Expand Up @@ -11,14 +11,25 @@ void TEST_CASE1() {
VSET(16, e8, m1);
__asm__ volatile("vid.v v1");
VCMP_U8(1, v1, 0, 1, 2, 3, 4, 5, 6, 7);
VSET(10, e8, m1);

VLOAD_8(v1, 0b00001110, 0b00000111, 0b00010000, 0b01001011, 0b00110100,
0b01111101, 0b11001100, 0b00011000, 0b01000111, 0b00010100);
VSET(77, e8, m1);
asm volatile("vid.v v2");
VCMP_U8(2, v2, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
69, 70, 71, 72, 73, 74, 75, 76);
}

void TEST_CASE2() {
VSET(16, e8, m1);
VLOAD_8(v0, 85, 0, 0, 0, 0, 0, 0, 0);
VCLEAR(v1);
__asm__ volatile("vid.v v1, v0.t");
VCMP_U8(2, v1, 0, 0, 2, 0, 4, 0, 6, 0);
VCMP_U8(3, v1, 0, 0, 2, 0, 4, 0, 6, 0);
}

int main(void) {
Expand Down
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