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Add VCU118 Support to mp/pulp-v1-os-fpga Branch #362

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Add VCU118 Support to mp/pulp-v1-os-fpga Branch #362

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0b0323c
Add VCU118 support to pulp-v1-os-fpga
Oct 4, 2024
8e8eb6f
Add VCU118 support to pulp-v1-os-fpga
Oct 4, 2024
57128f9
Switch to default clang and clang++ compilers
Oct 11, 2024
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24 changes: 14 additions & 10 deletions cheshire/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
#
# Author: Moritz Imfeld <[email protected]>
# Author: Matteo Perotti <[email protected]>
#
# Modifier : Mojtaba Rostami <[email protected]>

# Chshire root reposiotry
# Cheshire root repository
MAKEFILE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
ARA_ROOT := $(MAKEFILE_DIR)/..
BACKREF_CHS_ROOT ?= $(realpath ../../../../..)
Expand All @@ -20,18 +20,21 @@ VIVADO ?= 'vitis-2020.2 vivado'
# default configuration for Cheshire + Ara is 2_lanes
ARA_CONFIGURATION ?= 2_lanes
include $(ARA_ROOT)/config/$(ARA_CONFIGURATION).mk
BOARD := vcu128

# Default to VCU128 if no BOARD is specified, but allow overriding.
BOARD ?= vcu128
VLOG_ARGS ?= -suppress 2583 -suppress 13314
COMMON_CUSTOM_TARGETS := -t cv64a6_imafdcv_sv39 -t cva6 --define ARA --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen)
CUSTOM_SIM_BENDER_TARGETS := $(COMMON_CUSTOM_TARGETS) -t sim -t test -t rtl --vlog-arg="$(VLOG_ARGS)"
CUSTOM_XIL_BENDER_TARGETS := $(COMMON_CUSTOM_TARGETS) -t fpga -t $(BOARD)
CUSTOM_XIL_BENDER_TARGETS := $(COMMON_CUSTOM_TARGETS) -t fpga -t $(BOARD)

.PHONY: ara-chs-xilinx-$(BOARD) ara-chs-flash-$(BOARD) apply-patches update_xilinx_src clean
.PHONY: ara-chs-xilinx ara-chs-flash apply-patches update_xilinx_src clean

ara-chs-xilinx-$(BOARD): update_xilinx_src
# Combine the xilinx and flash targets to be flexible for different boards.
ara-chs-xilinx: update_xilinx_src
make -C $(BACKREF_CHS_ROOT) chs-xilinx-$(BOARD)

ara-chs-flash-$(BOARD):
ara-chs-flash:
make -C $(BACKREF_CHS_ROOT) chs-xilinx-flash-$(BOARD) VIVADO=$(VIVADO)

apply-patches:
Expand All @@ -40,13 +43,14 @@ apply-patches:

update_xilinx_src:
cd $(BACKREF_CHS_ROOT) && \
bender script vivado $(CUSTOM_XIL_BENDER_TARGETS) > $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.vcu128.tcl
bender script vivado $(CUSTOM_XIL_BENDER_TARGETS) > $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.$(BOARD).tcl

update_vsim_src:
cd $(BACKREF_CHS_ROOT) && \
bender script vsim $(CUSTOM_SIM_BENDER_TARGETS) > $(BACKREF_CHS_SIM_SCRIPTS)/compile.cheshire_soc.tcl
echo 'vlog "$(realpath $(BACKREF_CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $(BACKREF_CHS_SIM_SCRIPTS)/compile.cheshire_soc.tcl

clean:
rm $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.vcu128.tcl
rm $(MAKEFILE_DIR)/add_sources.vcu128.tcl
rm -f $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.$(BOARD).tcl
rm -f $(MAKEFILE_DIR)/add_sources.$(BOARD).tcl

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