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[HW/SW] Cheshire integration - Linux on FPGA #319

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88d9fd7
Add back-referencing bitstream compile flow to Cheshire
moimfeld Jul 1, 2024
51e6df2
Fix back reference target
moimfeld Jul 1, 2024
7831b1f
Change target from -all to -vcu128
moimfeld Jul 1, 2024
9ae15ac
Add ARA_CONFIGURATION parameter to cheshire/Makefile
moimfeld Jul 1, 2024
2abeba6
[cheshire/sw] Add basic software support for Cheshire
mp-17 Jul 5, 2024
9ca2d45
[cheshire] Fix relative path in makefile
mp-17 Jul 5, 2024
c1e26f1
[cheshire] Back-ref sw compilation flow for fmatmul
mp-17 Jul 5, 2024
290031f
Expose cheshire FPGA flash target to Ara
moimfeld Jul 14, 2024
f50ac2e
Add device tree patch for cheshire
moimfeld Jul 14, 2024
1c02941
Add backreferencing for simulation of Cheshire + Ara
moimfeld Jul 18, 2024
75a27f9
[cheshire] Add cva6-sdk submodule
mp-17 Oct 10, 2024
e43fe96
[cheshire] Add RVV-Linux img compilation flow
mp-17 Oct 10, 2024
7751af2
[ci] Bump upload artifact action to v4
mp-17 Oct 12, 2024
7d445b1
[apps] Enable LINUX compilation for apps
mp-17 Oct 15, 2024
91368b1
[cheshire] Add LINUX + SW flow for cheshire
mp-17 Oct 15, 2024
290d6b1
[Bender] Bump CVA6 to official PR
mp-17 Oct 15, 2024
9e219b3
[cheshire] Parametrize FPGA flow
Oct 15, 2024
f27f68f
[cheshire] Update READMEs
mp-17 Oct 16, 2024
024686d
[cheshire] Add config parametrization to RVV kernels
mp-17 Oct 16, 2024
5a48a30
[hardware] :bug: Fix vector slicing in operand requester
mp-17 Oct 8, 2024
8f7c121
[CHANGELOG] Update Changelog
mp-17 Oct 16, 2024
066896a
[cheshire] :bug: Quote variables in Makefile
mp-17 Oct 19, 2024
1998546
[cheshire] Copy install64 instead of softlinking
mp-17 Oct 19, 2024
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[CHANGELOG] Update Changelog
mp-17 committed Oct 16, 2024
commit 8f7c1218d50c6778e714b010202393759ecb21f2
6 changes: 6 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -23,6 +23,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Fix `acc_dispatcher` CVA6 bug for instructions with side effects
- Fix NaN/subnormal floating-point handling in opqueues
- Stall vfdiv/vfsqrt instructions following/preceding other fp instructions
- Fix vector slicing in the operand requesters

### Added

@@ -34,6 +35,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Add virtual->physical address translation for Ara by sharing CVA6 MMU
- Add Ara VLSU support for MMU exceptions
- Add multi-precision conv3d
- Add Cheshire bare-metal FPGA flow for vcu128 and vcu118
- Add cva6-sdk submodule
- Add Cheshire Linux FPGA flow for vcu128 and vcu118

### Changed

@@ -56,6 +60,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Memory size is now constant with NrLanes
- Enable hierarchical verilation
- Bump AXI and common cells to solve verilation warnings
- Update all Github Actions for CI
- Update READMEs with FPGA implementation instructions

## 3.0.0 - 2023-09-08

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