[apps] Add vrgather and vcompress tests

pulp-platform · Nov 25, 2024 · fd96b2d · fd96b2d
1 parent 535a52c
commit fd96b2d
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Showing 3 changed files with 96 additions and 26 deletions.
diff --git a/apps/riscv-tests/isa/rv64uv/Makefrag b/apps/riscv-tests/isa/rv64uv/Makefrag
@@ -178,9 +178,11 @@ rv64uv_sc_tests = vaadd \
                   vse64 \
                   vle_vse_hazards \
                   vfrec7 \
-                  vfrsqrt7
+                  vfrsqrt7 \
+                  vrgather \
+                  vcompress
 
-#rv64uv_sc_tests = vcompress vlff vrgather
+#rv64uv_sc_tests = vlff
 
 rv64uv_p_tests = $(addprefix rv64uv-p-, $(rv64uv_sc_tests))
 

diff --git a/apps/riscv-tests/isa/rv64uv/vcompress.c b/apps/riscv-tests/isa/rv64uv/vcompress.c
@@ -1,4 +1,4 @@
-// Copyright 2021 ETH Zurich and University of Bologna.
+// Copyright 2024 ETH Zurich and University of Bologna.
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 //
@@ -11,16 +11,29 @@ void TEST_CASE1() {
   VSET(4, e64, m1);
   VLOAD_64(v4, 1, 2, 3, 4);
   VLOAD_64(v0, 12, 0, 0, 0);
-  CLEAR(v2);
-  __asm__ volatile("vcompress.vm v2, v4, v0");
-  DEBUG_64(v2);
-  VEC_CMP_64(1, v2, 3, 4, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vcompress.vm v2, v4, v0");
+  VCMP_U64(1, v2, 3, 4, 0, 0);
 }
 
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4,
+              5, 6, 7, 8,
+              9, 10, 11, 12,
+              13, 14, 15, 16);
+  VLOAD_8(v0, 0b10111100, 0b10111111, 0, 0, 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0);
+  VCLEAR(v2);
+  asm volatile("vcompress.vm v2, v4, v0");
+  VCMP_U8(2, v2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 16, 0, 0, 0, 0);
+}
+
+
 int main(void) {
   INIT_CHECK();
   enable_vec();
   enable_fp();
   TEST_CASE1();
+  TEST_CASE2();
   EXIT_CHECK();
 }