[fpga] 👌 Add Alveo U280 board and change config

ara.core

@@ -7,6 +7,7 @@ filesets:
         file_type: systemVerilogSource
         files:
             - fpga/src/xcvu9p.svh
+            - fpga/src/xcu280.svh
             - hardware/deps/axi/src/axi_pkg.sv
             - hardware/deps/axi/src/axi_intf.sv
             - hardware/deps/axi/include/axi/assign.svh: {is_include_file: true, include_path: hardware/deps/axi/include}
@@ -288,7 +289,12 @@ filesets:
     xcvu9p:
         files:
             - fpga/constraints/ara.xdc: {file_type: xdc}
-            - fpga/src/xilinx_ara_soc.sv: {file_type : systemVerilogSource}
+            - fpga/src/xilinx_ara_soc.sv: {file_type: systemVerilogSource}
+
+    xcu280:
+        files: 
+            - fpga/constraints/ara.xdc: {file_type: xdc}
+            - fpga/src/xilinx_ara_soc.sv: {file_type: systemVerilogSource}
 
     svtb:
         file_type: systemVerilogSource
@@ -313,18 +319,30 @@ targets:
                 xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, --timescale, 1ns/1ps, --define, NR_LANES=4, --define, RVV_ARIANE=1, --define, TARGET_ARA_TEST, --define, TARGET_ASIC, --define, TARGET_CVA6_TEST, --define, TARGET_RTL, --define, TARGET_SIMULATION, --define, TARGET_VSIM, --define, VLEN=4096, --define, WT_DCACHE=1]
         parameters: [PRELOAD]
         toplevel: [ara_tb]
-    synth:
+    synth: &synth
         description: Synthesize the design for an FPGA board
         filesets:
             - xilinx_sram
             - rtl
             - xilinx_synth
-            - xcvu9p
         default_tool: vivado
+        toplevel: [xilinx_ara_soc]
+    synth-xcvu9p:
+        <<: *synth
+        description: Synthesize the design for an FPGA board
+        filesets_append:
+            - xcvu9p
         tools:
           vivado:
             part: xcvu9p-flgb2104-2-e
-        toplevel: [xilinx_ara_soc]
+    synth-xcu280:
+        <<: *synth
+        description: Synthesize the design for an FPGA board
+        filesets_append:
+            - xcu280
+        tools:
+          vivado:
+            part: xcu280-fsvh2892-2l-e
 parameters:
     PRELOAD:
         datatype  : file

fpga/constraints/ara.xdc

@@ -1 +1 @@
-create_clock -period 10.000 -name clk_i [get_ports clk_i]
+create_clock -period 13.334 -name clk_i [get_ports clk_i]

fpga/scripts/run.tcl

@@ -1,4 +1,5 @@
 # read_verilog -sv {../src/ara_0/fpga/src/xcvu9p.svh }
 # set file "../src/ara_0/fpga/src/xcvu9p.svh"
 
-set_property is_global_include true [get_files xcvu9p.svh]
+set_property is_global_include true [get_files xcvu9p.svh]
+set_property is_global_include true [get_files xcu280.svh]

fpga/src/xcu280.svh

@@ -0,0 +1,23 @@
+// Description: Set global FPGA degines
+// Author: Elisabeth Humblet [email protected]
+
+`define xcu280
+
+//=============================================================================
+// CVA6 Configurations
+//=============================================================================
+`define ARIANE_DATA_WIDTH 64
+// Instantiate protocl checker
+// `define PROTOCOL_CHECKER
+// write-back cache
+// `define WB_DCACHE
+// write-through cache
+`define WT_DCACHE 1
+
+`define RVV_ARIANE 1
+
+//=============================================================================
+// Ara Configurations
+//=============================================================================
+`define NrLanes 4
+`define VLEN 4096

fpga/src/xilinx_ara_soc.sv

@@ -24,7 +24,7 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #(
     parameter  int           unsigned AxiUserWidth = 1,
     parameter  int           unsigned AxiIdWidth   = 5,
     // Main memory
-    parameter  int           unsigned L2NumWords   = 2**14,
+    parameter  int           unsigned L2NumWords   = 2**15,
     // Dependant parameters. DO NOT CHANGE!
     localparam type                   axi_data_t   = logic [AxiDataWidth-1:0],
     localparam type                   axi_strb_t   = logic [AxiDataWidth/8-1:0],