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[CHANGELOG] Update Changelog
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mp-17 committed Oct 16, 2024
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Expand Up @@ -34,6 +34,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Add virtual->physical address translation for Ara by sharing CVA6 MMU
- Add Ara VLSU support for MMU exceptions
- Add multi-precision conv3d
- Add Cheshire bare-metal FPGA flow for vcu128 and vcu118
- Add cva6-sdk submodule
- Add Cheshire Linux FPGA flow for vcu128 and vcu118

### Changed

Expand All @@ -56,6 +59,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Memory size is now constant with NrLanes
- Enable hierarchical verilation
- Bump AXI and common cells to solve verilation warnings
- Update all Github Actions for CI
- Update READMEs with FPGA implementation instructions

## 3.0.0 - 2023-09-08

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