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[hardware] WIP: vrgather/vcompress global
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@mp-17
mp-17 committed Nov 25, 2024
1 parent acb74f5 commit e7d56e1
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Showing 6 changed files with 202 additions and 99 deletions.
12 changes: 9 additions & 3 deletions hardware/src/ara.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -331,6 +331,9 @@ module ara import ara_pkg::*; #(
strb_t [NrLanes-1:0] masku_result_be;
logic [NrLanes-1:0] masku_result_gnt;
logic [NrLanes-1:0] masku_result_final_gnt;
logic [NrLanes-1:0] masku_vrgat_req_valid;
logic [NrLanes-1:0] masku_vrgat_req_ready;
vaddr_t masku_vrgat_addr;

for (genvar lane = 0; lane < NrLanes; lane++) begin: gen_lanes
lane #(
Expand Down Expand Up @@ -402,6 +405,9 @@ module ara import ara_pkg::*; #(
.masku_result_be_i (masku_result_be[lane] ),
.masku_result_gnt_o (masku_result_gnt[lane] ),
.masku_result_final_gnt_o (masku_result_final_gnt[lane] ),
.masku_vrgat_req_valid_i (masku_vrgat_req_valid[lane] ),
.masku_vrgat_req_ready_o (masku_vrgat_req_ready[lane] ),
.masku_vrgat_addr_i (masku_vrgat_addr ),
.mask_i (mask[lane] ),
.mask_valid_i (mask_valid[lane] & mask_valid_lane ),
.mask_ready_o (lane_mask_ready[lane] )
Expand Down Expand Up @@ -594,9 +600,9 @@ module ara import ara_pkg::*; #(
.masku_result_be_o (masku_result_be ),
.masku_result_gnt_i (masku_result_gnt ),
.masku_result_final_gnt_i(masku_result_final_gnt ),
.masku_vrgat_req_valid_o ( ),
.masku_vrgat_req_ready_i ('0 ),
.masku_vrgat_addr_o ( ),
.masku_vrgat_req_valid_o (masku_vrgat_req_valid ),
.masku_vrgat_req_ready_i (masku_vrgat_req_ready ),
.masku_vrgat_addr_o (masku_vrgat_addr ),
// Interface with the VFUs
.mask_o (mask ),
.mask_valid_o (mask_valid ),
Expand Down
5 changes: 4 additions & 1 deletion hardware/src/ara_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -235,7 +235,7 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
unique case (op) inside
[VADD:VWREDSUM] : vfu = VFU_Alu;
[VMUL:VFWREDOSUM] : vfu = VFU_MFpu;
[VMFEQ:VMXNOR] : vfu = VFU_MaskUnit;
[VMFEQ:VCOMPRESS] : vfu = VFU_MaskUnit;
[VLE:VLXE] : vfu = VFU_LoadUnit;
[VSE:VSXE] : vfu = VFU_StoreUnit;
[VSLIDEUP:VSLIDEDOWN]: vfu = VFU_SlideUnit;
Expand Down Expand Up @@ -265,6 +265,9 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
[VMSEQ:VMXNOR]:
for (int i = 0; i < NrVFUs; i++)
if (i == VFU_Alu || i == VFU_MaskUnit) target_vfus[i] = 1'b1;
[VRGATHER:VCOMPRESS]:
for (int i = 0; i < NrVFUs; i++)
if (i == VFU_Alu || i == VFU_MaskUnit) target_vfus[i] = 1'b1;
[VMFEQ:VMFGE]:
for (int i = 0; i < NrVFUs; i++)
if (i == VFU_MFpu || i == VFU_MaskUnit) target_vfus[i] = 1'b1;
Expand Down
6 changes: 6 additions & 0 deletions hardware/src/lane/lane.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
input strb_t masku_result_be_i,
output logic masku_result_gnt_o,
output logic masku_result_final_gnt_o,
input logic masku_vrgat_req_valid_i,
output logic masku_vrgat_req_ready_o,
input vaddr_t masku_vrgat_addr_i,
// Interface between the Mask unit and the VFUs
input strb_t mask_i,
input logic mask_valid_i,
Expand Down Expand Up @@ -337,6 +340,9 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.masku_result_be_i (masku_result_be_i ),
.masku_result_gnt_o (masku_result_gnt_o ),
.masku_result_final_gnt_o (masku_result_final_gnt_o),
.masku_vrgat_req_valid_i (masku_vrgat_req_valid_i ),
.masku_vrgat_req_ready_o (masku_vrgat_req_ready_o ),
.masku_vrgat_addr_i (masku_vrgat_addr_i ),
// Slide Unit
.sldu_result_req_i (sldu_result_req_i ),
.sldu_result_id_i (sldu_result_id_i ),
Expand Down
59 changes: 54 additions & 5 deletions hardware/src/lane/lane_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,12 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
input logic alu_ready_i,
input logic [NrVInsn-1:0] alu_vinsn_done_i,
input logic mfpu_ready_i,
input logic [NrVInsn-1:0] mfpu_vinsn_done_i
);
input logic [NrVInsn-1:0] mfpu_vinsn_done_i,
// Masku interface for vrgather/vcompress
input logic masku_vrgat_req_valid_i,
output logic masku_vrgat_req_ready_o,
input vaddr_t masku_vrgat_addr_i
);,

////////////////////////////
// Register the request //
Expand Down Expand Up @@ -153,6 +157,50 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
end
end

////////////////////
// VRGATHER FSM //
////////////////////

typedef enum logic {IDLE, REQUESTING} vrgat_state_e;
vrgat_state_e vrgat_state_d, vrgat_state_q;

vaddr_t masku_vrgat_addr_q;
logic masku_vrgat_req_ready_d, masku_vrgat_req_valid_q;

spill_register #(
.T ( vaddr_t )
) i_spill_register_vrgat_addr (
.clk_i,
.rst_ni,
.valid_i (masku_vrgat_req_valid_i),
.ready_o (masku_vrgat_req_ready_o),
.data_i (masku_vrgat_addr_i),
.valid_o (masku_vrgat_req_valid_q),
.ready_i (masku_vrgat_req_ready_d),
.data_o (masku_vrgat_addr_q)
);

always_comb begin
masku_vrgat_req_ready_d = 1'b0;

// If MASKU request arrives, wait until the MaskB requester is free
// Also, lock the MaskB opqueue
unique case (vrgat_state_q)
IDLE: begin
if (masku_vrgat_req_valid_q && !(operand_request_valid_o[MaskB])) begin
vrgat_state_d = REQUESTING;
end
end
REQUESTING: begin
// If the MASKU is over with VRGATHER/VCOMPRESS, return tu idle
if (masku_vrgat_end_q) begin
vrgat_state_d = IDLE;
end
end
default:;
endcase
end

/////////////////////////////
// VFU Operation control //
/////////////////////////////
Expand Down Expand Up @@ -231,7 +279,8 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
operand_request_valid_o[MaskM]);
end
VFU_None : begin
pe_req_ready = !(operand_request_valid_o[MaskB]);
// VRGATHER/VCOMPRESS use the MaskB opqueue with non-traditional request scheme
pe_req_ready = !(operand_request_valid_o[MaskB]) && ((vrgat_state_q == IDLE) && !masku_vrgat_req_valid_q);
end
default:;
endcase
Expand Down Expand Up @@ -652,13 +701,13 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
// extra operand regardless of whether it is valid in this lane or not.

// Integer comparisons run on the ALU and then get reshuffled and masked in the MASKU
if (pe_req.op inside {[VMSEQ:VMSBC]}) begin
if (pe_req.op inside {[VMSEQ:VMSBC],[VRGATHER:VRGATHEREI16]}) begin
// These source regs contain non-mask vectors.
operand_request[AluA].eew = pe_req.eew_vs1;
operand_request[AluA].vl = pe_req.vl / NrLanes;
if ((operand_request[AluA].vl * NrLanes) != pe_req.vl)
operand_request[AluA].vl += 1;
end else begin // Mask logical operations
end else begin // Mask logical operations or VCOMPRESS
// These source regs contain mask vectors.
operand_request[AluA].eew = EW64;
operand_request[AluA].vl = pe_req.vl / NrLanes / ELEN;
Expand Down
1 change: 1 addition & 0 deletions hardware/src/lane/operand_requester.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@ module operand_requester import ara_pkg::*; import rvv_pkg::*; #(
input strb_t masku_result_be_i,
output logic masku_result_gnt_o,
output logic masku_result_final_gnt_o,
output logic masku_result_final_gnt_o,
// Slide unit
input logic sldu_result_req_i,
input vid_t sldu_result_id_i,
Expand Down
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