[hardware] 🐛 Fix reshuffle

hardware/src/ara_dispatcher.sv

@@ -144,6 +144,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   // eew buffers for reshuffling
   rvv_pkg::vew_e reshuffle_eew_vs1_d, reshuffle_eew_vs1_q;
   rvv_pkg::vew_e reshuffle_eew_vs2_d, reshuffle_eew_vs2_q;
+  rvv_pkg::vew_e reshuffle_eew_vd_d, reshuffle_eew_vd_q;
   // If the reg was not written, the content is unknown. No need to reshuffle
   // when writing with != EEW
   logic [31:0] eew_valid_d, eew_valid_q;
@@ -172,6 +173,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
       rs_mask_request_q   <= 1'b0;
       reshuffle_eew_vs1_q <= rvv_pkg::EW8;
       reshuffle_eew_vs2_q <= rvv_pkg::EW8;
+      reshuffle_eew_vd_q  <= rvv_pkg::EW8;
     end else begin
       state_q             <= state_d;
       eew_q               <= eew_d;
@@ -185,6 +187,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
       rs_mask_request_q   <= rs_mask_request_d;
       reshuffle_eew_vs1_q <= reshuffle_eew_vs1_d;
       reshuffle_eew_vs2_q <= reshuffle_eew_vs2_d;
+      reshuffle_eew_vd_q  <= reshuffle_eew_vd_d;
     end
   end
 
@@ -260,6 +263,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
     vs_buffer_d         = vs_buffer_q;
     reshuffle_eew_vs1_d = reshuffle_eew_vs1_q;
     reshuffle_eew_vs2_d = reshuffle_eew_vs2_q;
+    reshuffle_eew_vd_d  = reshuffle_eew_vd_q;
 
     rs_lmul_cnt_d       = '0;
     rs_lmul_cnt_limit_d = '0;
@@ -387,6 +391,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
             // Prepare the information to reshuffle the vector registers during the next cycles
             // Reshuffle in the following order: vd, v2, v1. The order is arbitrary.
+            // If we are here, vd has been already reshuffled.
             unique casez (reshuffle_req_d)
               3'b?10: begin
                 eew_old_buffer_d = eew_q[insn.vmem_type.rs2];
@@ -427,17 +432,17 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
               3'b??1: begin
                 vs_buffer_d      = vs_buffer_q + 1;
                 eew_old_buffer_d = eew_q[vs_buffer_d];
-                eew_new_buffer_d = ara_req_d.vtype.vsew;
+                eew_new_buffer_d = reshuffle_eew_vd_q;
               end
               3'b?10: begin
                 vs_buffer_d      = vs_buffer_q + 1;
                 eew_old_buffer_d = eew_q[vs_buffer_d];
-                eew_new_buffer_d = ara_req_d.eew_vs2;
+                eew_new_buffer_d = reshuffle_eew_vs2_q;
               end
               3'b100: begin
                 vs_buffer_d      = vs_buffer_q + 1;
                 eew_old_buffer_d = eew_q[vs_buffer_d];
-                eew_new_buffer_d = ara_req_d.eew_vs1;
+                eew_new_buffer_d = reshuffle_eew_vs1_q;
               end
               default:;
             endcase
@@ -3240,6 +3245,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
         // Save info for next reshuffles
         reshuffle_eew_vs1_d = ara_req_d.eew_vs1;
         reshuffle_eew_vs2_d = ara_req_d.eew_vs2;
+        reshuffle_eew_vd_d  = ara_req_d.vtype.vsew;
 
         // Reshuffle
         state_d = RESHUFFLE;