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[hardware] Compress accelerator MMU interface
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@mp-17
mp-17 committed Jun 19, 2024
1 parent ba65fdc commit 915bb66
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Showing 3 changed files with 20 additions and 66 deletions.
39 changes: 12 additions & 27 deletions hardware/src/ara.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -41,24 +41,9 @@ module ara import ara_pkg::*; #(
// CSR input
input logic en_ld_st_translation_i,

// Interface with CVA6's sv39 MMU
// This is everything the MMU can provide, it might be overcomplete for Ara and some signals be useless
output ariane_pkg::exception_t mmu_misaligned_ex_o,
output logic mmu_req_o, // request address translation
output logic [riscv::VLEN-1:0] mmu_vaddr_o, // virtual address out
output logic mmu_is_store_o, // the translation is requested by a store
// if we need to walk the page table we can't grant in the same cycle
// Cycle 0
input logic mmu_dtlb_hit_i, // sent in the same cycle as the request if translation hits in the DTLB
input logic [riscv::PPNW-1:0] mmu_dtlb_ppn_i, // ppn (send same cycle as hit)
// Cycle 1
input logic mmu_valid_i, // translation is valid
input logic [riscv::PLEN-1:0] mmu_paddr_i, // translated address
input ariane_pkg::exception_t mmu_exception_i, // address translation threw an exception

// Interface with Ariane
input accelerator_req_t acc_req_i,
output accelerator_resp_t acc_resp_o,
input cva6_to_acc_t acc_req_i,
output acc_to_cva6_t acc_resp_o,
// AXI interface
output axi_req_t axi_req_o,
input axi_resp_t axi_resp_i
Expand Down Expand Up @@ -377,17 +362,17 @@ module ara import ara_pkg::*; #(
.addrgen_operand_valid_i (sldu_addrgen_operand_valid ),
.addrgen_operand_ready_o (addrgen_operand_ready ),
// CSR input
.en_ld_st_translation_i,
.en_ld_st_translation_i (acc_req_i.acc_mmu_en ),
// Interface with CVA6's sv39 MMU
.mmu_misaligned_ex_o ,
.mmu_req_o ,
.mmu_vaddr_o ,
.mmu_is_store_o ,
.mmu_dtlb_hit_i ,
.mmu_dtlb_ppn_i ,
.mmu_valid_i ,
.mmu_paddr_i ,
.mmu_exception_i ,
.mmu_misaligned_ex_o (acc_resp_o.mmu_misaligned_ex_o ),
.mmu_req_o (acc_resp_o.mmu_req_o ),
.mmu_vaddr_o (acc_resp_o.mmu_vaddr_o ),
.mmu_is_store_o (acc_resp_o.mmu_is_store_o ),
.mmu_dtlb_hit_i (acc_req_i.mmu_dtlb_hit_i ),
.mmu_dtlb_ppn_i (acc_req_i.mmu_dtlb_ppn_i ),
.mmu_valid_i (acc_req_i.mmu_valid_i ),
.mmu_paddr_i (acc_req_i.mmu_paddr_i ),
.mmu_exception_i (acc_req_i.mmu_exception_i ),
// Load unit
.ldu_result_req_o (ldu_result_req ),
.ldu_result_addr_o (ldu_result_addr ),
Expand Down
4 changes: 2 additions & 2 deletions hardware/src/ara_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
input logic clk_i,
input logic rst_ni,
// Interfaces with Ariane
input accelerator_req_t acc_req_i,
output accelerator_resp_t acc_resp_o,
input cva6_to_acc_t acc_req_i,
output acc_to_cva6_t acc_resp_o,
// Interface with Ara's backend
output ara_req_t ara_req_o,
output logic ara_req_valid_o,
Expand Down
43 changes: 6 additions & 37 deletions hardware/src/ara_system.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -73,12 +73,12 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
// Ara and Ariane //
//////////////////////

import acc_pkg::accelerator_req_t;
import acc_pkg::accelerator_resp_t;
import acc_pkg::cva6_to_acc_t;
import acc_pkg::acc_to_cva6_t;

// Accelerator ports
accelerator_req_t acc_req;
accelerator_resp_t acc_resp;
cva6_to_acc_t acc_req;
acc_to_cva6_t acc_resp;
logic acc_resp_valid;
logic acc_resp_ready;
logic acc_cons_en;
Expand All @@ -100,17 +100,6 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
acc_cons_en = acc_req.acc_cons_en;
end

logic en_ld_st_translation;
ariane_pkg::exception_t mmu_misaligned_ex;
logic mmu_req;
logic [riscv::VLEN-1:0] mmu_vaddr;
logic mmu_is_store;
logic mmu_dtlb_hit;
logic [riscv::PPNW-1:0] mmu_dtlb_ppn;
logic mmu_valid;
logic [riscv::PLEN-1:0] mmu_paddr;
ariane_pkg::exception_t mmu_exception;

`ifdef IDEAL_DISPATCHER
// Perfect dispatcher to Ara
accel_dispatcher_ideal i_accel_dispatcher_ideal (
Expand All @@ -124,8 +113,8 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
`else
cva6 #(
.CVA6Cfg (CVA6Cfg ),
.cvxif_req_t (acc_pkg::accelerator_req_t ),
.cvxif_resp_t (acc_pkg::accelerator_resp_t),
.cvxif_req_t (acc_pkg::cva6_to_acc_t ),
.cvxif_resp_t (acc_pkg::acc_to_cva6_t ),
.axi_ar_chan_t (ariane_axi_ar_t ),
.axi_aw_chan_t (ariane_axi_aw_t ),
.axi_w_chan_t (ariane_axi_w_t ),
Expand All @@ -150,16 +139,6 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
.clic_irq_ready_o (/* empty */ ),
.clic_kill_req_i ('0 ),
.clic_kill_ack_o (/* empty */ ),
.en_ld_st_translation_o (en_ld_st_translation ),
.acc_mmu_misaligned_ex_i(mmu_misaligned_ex),
.acc_mmu_req_i (mmu_req ),
.acc_mmu_vaddr_i (mmu_vaddr ),
.acc_mmu_is_store_i (mmu_is_store ),
.acc_mmu_dtlb_hit_o (mmu_dtlb_hit ),
.acc_mmu_dtlb_ppn_o (mmu_dtlb_ppn ),
.acc_mmu_valid_o (mmu_valid ),
.acc_mmu_paddr_o (mmu_paddr ),
.acc_mmu_exception_o (mmu_exception ),
.rvfi_probes_o (/* empty */ ),
// Accelerator ports
.cvxif_req_o (acc_req ),
Expand Down Expand Up @@ -247,16 +226,6 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
.scan_enable_i (scan_enable_i ),
.scan_data_i (1'b0 ),
.scan_data_o (/* Unused */ ),
.en_ld_st_translation_i(en_ld_st_translation),
.mmu_misaligned_ex_o(mmu_misaligned_ex),
.mmu_req_o(mmu_req),
.mmu_vaddr_o(mmu_vaddr),
.mmu_is_store_o(mmu_is_store),
.mmu_dtlb_hit_i(mmu_dtlb_hit),
.mmu_dtlb_ppn_i(mmu_dtlb_ppn),
.mmu_valid_i(mmu_valid),
.mmu_paddr_i(mmu_paddr),
.mmu_exception_i(mmu_exception),
.acc_req_i (acc_req ),
.acc_resp_o (acc_resp ),
.axi_req_o (ara_axi_req ),
Expand Down

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