[cheshire] Parametrize FPGA flow

The flow now also works with VCU11

cheshire/Makefile

@@ -2,9 +2,9 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #
-# Author: Moritz Imfeld  <[email protected]>
-# Author: Matteo Perotti <[email protected]>
-#
+# Author: Moritz Imfeld   <[email protected]>
+# Author: Matteo Perotti  <[email protected]>
+# Author: Mojtaba Rostami <[email protected]>
 
 # Chshire root reposiotry
 MAKEFILE_DIR            := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
@@ -20,7 +20,7 @@ VIVADO ?= 'vitis-2020.2 vivado'
 # default configuration for Cheshire + Ara is 2_lanes
 ARA_CONFIGURATION         ?= 2_lanes
 include $(ARA_ROOT)/config/$(ARA_CONFIGURATION).mk
-BOARD                     := vcu128
+BOARD                     ?= vcu128
 VLOG_ARGS                 ?= -suppress 2583 -suppress 13314
 COMMON_CUSTOM_TARGETS     := -t cv64a6_imafdcv_sv39 -t cva6 --define ARA --define NR_LANES=$(nr_lanes) --define VLEN=$(vlen)
 CUSTOM_SIM_BENDER_TARGETS := $(COMMON_CUSTOM_TARGETS) -t sim -t test -t rtl --vlog-arg="$(VLOG_ARGS)"
@@ -30,29 +30,29 @@ CUSTOM_XIL_BENDER_TARGETS := $(COMMON_CUSTOM_TARGETS) -t fpga -t $(BOARD)
 CHS_XILINX_HWS_URL  ?=
 CHS_XILINX_HWS_PATH ?=
 
-.PHONY: ara-chs-xilinx-$(BOARD) ara-chs-flash-$(BOARD) ara-chs-xilinx-program-$(BOARD) update_xilinx_src update_vsim_src clean
+.PHONY: ara-chs-xilinx ara-chs-flash ara-chs-xilinx-program update_xilinx_src update_vsim_src clean
 
-ara-chs-xilinx-$(BOARD): update_xilinx_src
+ara-chs-xilinx: update_xilinx_src
 	make -C $(BACKREF_CHS_ROOT) chs-xilinx-$(BOARD)
 
-ara-chs-image-$(BOARD):
+ara-chs-image:
 	make -C $(BACKREF_CHS_ROOT) $(BACKREF_CHS_ROOT)/sw/boot/linux.$(BOARD).gpt.bin -B
 
-ara-chs-xilinx-flash-$(BOARD):
+ara-chs-xilinx-flash:
 	make -C $(BACKREF_CHS_ROOT) chs-xilinx-flash-$(BOARD) VIVADO=$(VIVADO) CHS_XILINX_HWS_URL=$(CHS_XILINX_HWS_URL) CHS_XILINX_HWS_PATH_$(BOARD)=$(CHS_XILINX_HWS_PATH)
 
-ara-chs-xilinx-program-$(BOARD):
+ara-chs-xilinx-program:
 	make -C $(BACKREF_CHS_ROOT) chs-xilinx-program-$(BOARD) VIVADO=$(VIVADO) CHS_XILINX_HWS_URL=$(CHS_XILINX_HWS_URL) CHS_XILINX_HWS_PATH_$(BOARD)=$(CHS_XILINX_HWS_PATH)
 
 update_xilinx_src:
 	cd $(BACKREF_CHS_ROOT) && \
-	bender script vivado $(CUSTOM_XIL_BENDER_TARGETS) > $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.vcu128.tcl
+	bender script vivado $(CUSTOM_XIL_BENDER_TARGETS) > $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.$(BOARD).tcl
 
 update_vsim_src:
 	cd $(BACKREF_CHS_ROOT) && \
 	bender script vsim $(CUSTOM_SIM_BENDER_TARGETS) > $(BACKREF_CHS_SIM_SCRIPTS)/compile.cheshire_soc.tcl
 	echo 'vlog "$(realpath $(BACKREF_CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $(BACKREF_CHS_SIM_SCRIPTS)/compile.cheshire_soc.tcl
 
 clean:
-	rm $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.vcu128.tcl
-	rm $(MAKEFILE_DIR)/add_sources.vcu128.tcl
+	rm $(BACKREF_CHS_XIL_SCRIPTS)/add_sources.$(BOARD).tcl
+	rm $(MAKEFILE_DIR)/add_sources.$(BOARD).tcl