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Mask Unit clean-up
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Signed-off-by: Moritz Imfeld <[email protected]>
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@moimfeld @mp-17
moimfeld authored and mp-17 committed Nov 8, 2024
1 parent 314546b commit 6671a5e
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Showing 5 changed files with 523 additions and 351 deletions.
3 changes: 2 additions & 1 deletion Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ sources:
- hardware/src/lane/simd_mul.sv
- hardware/src/lane/vector_regfile.sv
- hardware/src/lane/power_gating_generic.sv
- hardware/src/masku/masku.sv
- hardware/src/masku/masku_operands.sv
- hardware/src/sldu/p2_stride_gen.sv
- hardware/src/sldu/sldu_op_dp.sv
- hardware/src/sldu/sldu.sv
Expand All @@ -54,6 +54,7 @@ sources:
- hardware/src/lane/vmfpu.sv
- hardware/src/lane/fixed_p_rounding.sv
- hardware/src/vlsu/vlsu.sv
- hardware/src/masku/masku.sv
# Level 3
- hardware/src/lane/vector_fus_stage.sv
# Level 4
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33 changes: 0 additions & 33 deletions hardware/src/ara_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -588,7 +588,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b010001: begin
ara_req_d.op = ara_pkg::VMADC;
ara_req_d.use_vd_op = 1'b1;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
Expand Down Expand Up @@ -618,7 +617,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b010011: begin
ara_req_d.op = ara_pkg::VMSBC;
ara_req_d.use_vd_op = 1'b1;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
Expand All @@ -641,27 +639,21 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b011000: begin
ara_req_d.op = ara_pkg::VMSEQ;
ara_req_d.use_vd_op = 1'b1;
end
6'b011001: begin
ara_req_d.op = ara_pkg::VMSNE;
ara_req_d.use_vd_op = 1'b1;
end
6'b011010: begin
ara_req_d.op = ara_pkg::VMSLTU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011011: begin
ara_req_d.op = ara_pkg::VMSLT;
ara_req_d.use_vd_op = 1'b1;
end
6'b011100: begin
ara_req_d.op = ara_pkg::VMSLEU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011101: begin
ara_req_d.op = ara_pkg::VMSLE;
ara_req_d.use_vd_op = 1'b1;
end
6'b010111: begin
ara_req_d.op = ara_pkg::VMERGE;
Expand Down Expand Up @@ -828,7 +820,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b010001: begin
ara_req_d.op = ara_pkg::VMADC;
ara_req_d.use_vd_op = 1'b1;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
Expand All @@ -855,7 +846,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b010011: begin
ara_req_d.op = ara_pkg::VMSBC;
ara_req_d.use_vd_op = 1'b1;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
Expand All @@ -873,35 +863,27 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b011000: begin
ara_req_d.op = ara_pkg::VMSEQ;
ara_req_d.use_vd_op = 1'b1;
end
6'b011001: begin
ara_req_d.op = ara_pkg::VMSNE;
ara_req_d.use_vd_op = 1'b1;
end
6'b011010: begin
ara_req_d.op = ara_pkg::VMSLTU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011011: begin
ara_req_d.op = ara_pkg::VMSLT;
ara_req_d.use_vd_op = 1'b1;
end
6'b011100: begin
ara_req_d.op = ara_pkg::VMSLEU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011101: begin
ara_req_d.op = ara_pkg::VMSLE;
ara_req_d.use_vd_op = 1'b1;
end
6'b011110: begin
ara_req_d.op = ara_pkg::VMSGTU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011111: begin
ara_req_d.op = ara_pkg::VMSGT;
ara_req_d.use_vd_op = 1'b1;
end
6'b010111: begin
ara_req_d.op = ara_pkg::VMERGE;
Expand Down Expand Up @@ -1034,7 +1016,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b010001: begin
ara_req_d.op = ara_pkg::VMADC;
ara_req_d.use_vd_op = 1'b1;

// Check whether we can access vs1 and vs2
unique case (ara_req_d.emul)
Expand All @@ -1052,27 +1033,21 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
end
6'b011000: begin
ara_req_d.op = ara_pkg::VMSEQ;
ara_req_d.use_vd_op = 1'b1;
end
6'b011001: begin
ara_req_d.op = ara_pkg::VMSNE;
ara_req_d.use_vd_op = 1'b1;
end
6'b011100: begin
ara_req_d.op = ara_pkg::VMSLEU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011101: begin
ara_req_d.op = ara_pkg::VMSLE;
ara_req_d.use_vd_op = 1'b1;
end
6'b011110: begin
ara_req_d.op = ara_pkg::VMSGTU;
ara_req_d.use_vd_op = 1'b1;
end
6'b011111: begin
ara_req_d.op = ara_pkg::VMSGT;
ara_req_d.use_vd_op = 1'b1;
end
6'b010111: begin
ara_req_d.op = ara_pkg::VMERGE;
Expand Down Expand Up @@ -1322,63 +1297,55 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011001: begin
ara_req_d.op = ara_pkg::VMAND;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011010: begin
ara_req_d.op = ara_pkg::VMOR;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011011: begin
ara_req_d.op = ara_pkg::VMXOR;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011100: begin
ara_req_d.op = ara_pkg::VMORNOT;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011101: begin
ara_req_d.op = ara_pkg::VMNAND;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011110: begin
ara_req_d.op = ara_pkg::VMNOR;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b011111: begin
ara_req_d.op = ara_pkg::VMXNOR;
ara_req_d.eew_vs1 = EW8;
ara_req_d.eew_vs2 = EW8;
ara_req_d.eew_vd_op = EW8;
ara_req_d.vtype.vsew = EW8;
ara_req_d.use_vd_op = 1'b1;
end
6'b010010: begin // VXUNARY0
// These instructions do not use vs1
Expand Down
22 changes: 12 additions & 10 deletions hardware/src/lane/lane_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -667,7 +667,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
if ((operand_request[AluA].vl << (unsigned'(EW64) - unsigned'(pe_req.eew_vs1))) * NrLanes !=
pe_req.vl) operand_request[AluA].vl += 1;
end
operand_request_push[AluA] = pe_req.use_vs1 && !(pe_req.op inside {[VMFEQ:VMFGE]});
operand_request_push[AluA] = pe_req.use_vs1 && !(pe_req.op inside {[VMFEQ:VMFGE], VCPOP, VMSIF, VMSOF, VMSBF});

operand_request[AluB] = '{
id : pe_req.id,
Expand All @@ -694,7 +694,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
if ((operand_request[AluB].vl << (unsigned'(EW64) - unsigned'(pe_req.eew_vs2))) * NrLanes !=
pe_req.vl) operand_request[AluB].vl += 1;
end
operand_request_push[AluB] = pe_req.use_vs2 && !(pe_req.op inside {[VMFEQ:VMFGE]});
operand_request_push[AluB] = pe_req.use_vs2 && !(pe_req.op inside {[VMFEQ:VMFGE], VCPOP, VMSIF, VMSOF, VMSBF, VFIRST});

operand_request[MulFPUA] = '{
id : pe_req.id,
Expand All @@ -710,7 +710,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
// This is an operation that runs normally on the ALU, and then gets *condensed* and
// reshuffled at the Mask Unit.
operand_request[MulFPUA].vl = vfu_operation_d.vl;
operand_request_push[MulFPUA] = pe_req.use_vs1 && pe_req.op inside {[VMFEQ:VMFGE]};
operand_request_push[MulFPUA] = pe_req.use_vs1 && pe_req.op inside {[VMFEQ:VMFGE]} && !(pe_req.op inside {VCPOP, VMSIF, VMSOF, VMSBF});

operand_request[MulFPUB] = '{
id : pe_req.id,
Expand All @@ -725,24 +725,26 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
// This is an operation that runs normally on the ALU, and then gets *condensed* and
// reshuffled at the Mask Unit.
operand_request[MulFPUB].vl = vfu_operation_d.vl;
operand_request_push[MulFPUB] = pe_req.use_vs2 && pe_req.op inside {[VMFEQ:VMFGE]};
operand_request_push[MulFPUB] = pe_req.use_vs2 && pe_req.op inside {[VMFEQ:VMFGE]} && !(pe_req.op inside {VCPOP, VMSIF, VMSOF, VMSBF, VFIRST});

operand_request[MaskB] = '{
id : pe_req.id,
vs : pe_req.vd,
eew : pe_req.eew_vd_op,
vs : pe_req.vs2,
eew : pe_req.eew_vs2,
scale_vl: pe_req.scale_vl,
vtype : pe_req.vtype,
// Since this request goes outside of the lane, we might need to request an
// extra operand regardless of whether it is valid in this lane or not.
vl : (pe_req.vl / NrLanes / ELEN) << (unsigned'(EW64) - unsigned'(pe_req.vtype.vsew)),
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vd,
hazard : (pe_req.op inside {VMSBF, VMSOF, VMSIF}) ? pe_req.hazard_vs2 : pe_req.hazard_vs2 | pe_req.hazard_vd,
default : '0
};
if (((pe_req.vl / NrLanes / ELEN) * NrLanes * ELEN) !=
pe_req.vl) operand_request[MaskB].vl += 1;
operand_request_push[MaskB] = pe_req.use_vd_op;
operand_request[MaskB].vl = pe_req.vl / (NrLanes * (8 << pe_req.vtype.vsew));
if ((pe_req.vl % (NrLanes*ELEN)) != 0) begin
operand_request[MaskB].vl += 1'b1;
end
operand_request_push[MaskB] = pe_req.use_vs2 && pe_req.op inside {VCPOP, VFIRST, VMSIF, VMSOF, VMSBF};

operand_request[MaskM] = '{
id : pe_req.id,
Expand Down
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