[hardware] Remove vl-mask for mask tail elements

Mask-producing insn can avoid worrying of tail elements
pulp-platform · Oct 30, 2024 · 5b508b3 · 5b508b3
1 parent 8aec02c
commit 5b508b3
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Showing 2 changed files with 5 additions and 11 deletions.
diff --git a/hardware/src/masku/masku.sv b/hardware/src/masku/masku.sv
@@ -105,7 +105,6 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
   pe_req_t vinsn_issue;
 
   logic  [NrLanes*ELEN-1:0] bit_enable_mask;
-  logic  [NrLanes*ELEN-1:0] bit_enable_shuffle;
   logic  [NrLanes*ELEN-1:0] alu_result_compressed;
 
   // Performs all shuffling and deshuffling of mask operands (including masks for mask instructions)
@@ -143,7 +142,6 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
     .masku_operand_m_seq_valid_o   (  ),
     .masku_operand_m_seq_ready_i   (  ),
     .bit_enable_mask_o             (             bit_enable_mask ),
-    .shuffled_vl_bit_mask_o        (          bit_enable_shuffle ),
     .alu_result_compressed_o       (       alu_result_compressed )
   );
 
@@ -447,8 +445,8 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
 
       // Evaluate the instruction
       unique case (vinsn_issue.op) inside
-        [VMANDNOT:VMXNOR]: alu_result = (masku_operand_alu) | (~bit_enable_shuffle);
-        [VMFEQ:VMSGTU], [VMSGT:VMSBC]:  alu_result = (alu_result_compressed & bit_enable_mask) | (~bit_enable_shuffle);
+        [VMANDNOT:VMXNOR]: alu_result = masku_operand_alu;
+        [VMFEQ:VMSGTU], [VMSGT:VMSBC]: alu_result = alu_result_compressed & bit_enable_mask;
         [VMSBF:VMSIF] : begin
             if (&masku_operand_vs2_seq_valid && (&masku_operand_m_valid || vinsn_issue.vm)) begin
               for (int i = 0; i < NrLanes * DataWidth; i++) begin
@@ -750,7 +748,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
             ((vcpop_slice_cnt_q == N_SLICES_VFIRST-1) && vinsn_issue.op == VFIRST)) begin
           vcpop_slice_cnt_d       = '0;
           vcpop_vfirst_vs2_ready = masku_operand_vs2_seq_valid;
-          if (!vinsn_issue.vm) begin 
+          if (!vinsn_issue.vm) begin
             masku_operand_m_ready = '1;
           end
         end
@@ -764,7 +762,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
           commit_cnt_d = '0;
           read_cnt_d ='0;
           vcpop_vfirst_vs2_ready = masku_operand_vs2_seq_valid;
-          if (!vinsn_issue.vm) begin 
+          if (!vinsn_issue.vm) begin
             masku_operand_m_ready = '1;
           end
         end
@@ -788,7 +786,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
 
           // acknowledge operand a
           vcpop_vfirst_vs2_ready = masku_operand_vs2_seq_valid;
-          if (!vinsn_issue.vm) begin 
+          if (!vinsn_issue.vm) begin
             masku_operand_m_ready = '1;
           end
         end

diff --git a/hardware/src/masku/masku_operands.sv b/hardware/src/masku/masku_operands.sv
@@ -52,7 +52,6 @@ module masku_operands import ara_pkg::*; import rvv_pkg::*; #(
     output logic  [     NrLanes-1:0] masku_operand_m_seq_valid_o,
     input  logic  [     NrLanes-1:0] masku_operand_m_seq_ready_i,
     output logic  [NrLanes*ELEN-1:0] bit_enable_mask_o,       // Bit mask for mask unit instructions (shuffled like mask register)
-    output logic  [NrLanes*ELEN-1:0] shuffled_vl_bit_mask_o,  // vl mask for mask unit instructions (first vl bits are 1, others 0)  (shuffled like mask register)
     output logic  [NrLanes*ELEN-1:0] alu_result_compressed_o  // ALU/FPU results compressed (from sew to 1-bit) (shuffled, in mask format)
   );
 
@@ -179,9 +178,6 @@ module masku_operands import ara_pkg::*; import rvv_pkg::*; #(
     end
   end
 
-  assign shuffled_vl_bit_mask_o = shuffled_vl_bit_mask;
-
-
   // -------------------------------------------
   // Compress ALU/FPU results into a mask vector
   // -------------------------------------------