[hardware] Compress accelerator MMU interface

pulp-platform · Jun 24, 2024 · 48cc83e · 48cc83e
1 parent b4df5fd
commit 48cc83e
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Showing 3 changed files with 20 additions and 35 deletions.
diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv
@@ -41,24 +41,9 @@ module ara import ara_pkg::*; #(
     // CSR input
     input  logic              en_ld_st_translation_i,
 
-    // Interface with CVA6's sv39 MMU
-    // This is everything the MMU can provide, it might be overcomplete for Ara and some signals be useless
-    output  ariane_pkg::exception_t        mmu_misaligned_ex_o,
-    output  logic                          mmu_req_o,        // request address translation
-    output  logic [riscv::VLEN-1:0]        mmu_vaddr_o,      // virtual address out
-    output  logic                          mmu_is_store_o,   // the translation is requested by a store
-    // if we need to walk the page table we can't grant in the same cycle
-    // Cycle 0
-    input logic                            mmu_dtlb_hit_i,   // sent in the same cycle as the request if translation hits in the DTLB
-    input logic [riscv::PPNW-1:0]          mmu_dtlb_ppn_i,   // ppn (send same cycle as hit)
-    // Cycle 1
-    input logic                            mmu_valid_i,      // translation is valid
-    input logic [riscv::PLEN-1:0]          mmu_paddr_i,      // translated address
-    input ariane_pkg::exception_t          mmu_exception_i,  // address translation threw an exception
-
     // Interface with Ariane
-    input  accelerator_req_t  acc_req_i,
-    output accelerator_resp_t acc_resp_o,
+    input  cva6_to_acc_t  acc_req_i,
+    output acc_to_cva6_t  acc_resp_o,
     // AXI interface
     output axi_req_t          axi_req_o,
     input  axi_resp_t         axi_resp_i
@@ -377,17 +362,17 @@ module ara import ara_pkg::*; #(
     .addrgen_operand_valid_i    (sldu_addrgen_operand_valid                            ),
     .addrgen_operand_ready_o    (addrgen_operand_ready                                 ),
     // CSR input
-    .en_ld_st_translation_i,
+    .en_ld_st_translation_i     (acc_req_i.acc_mmu_en                                  ),
     // Interface with CVA6's sv39 MMU
-    .mmu_misaligned_ex_o   ,
-    .mmu_req_o             ,
-    .mmu_vaddr_o           ,
-    .mmu_is_store_o        ,
-    .mmu_dtlb_hit_i        ,
-    .mmu_dtlb_ppn_i        ,
-    .mmu_valid_i           ,
-    .mmu_paddr_i           ,
-    .mmu_exception_i       ,
+    .mmu_misaligned_ex_o        (acc_resp_o.mmu_misaligned_ex_o                        ),
+    .mmu_req_o                  (acc_resp_o.mmu_req_o                                  ),
+    .mmu_vaddr_o                (acc_resp_o.mmu_vaddr_o                                ),
+    .mmu_is_store_o             (acc_resp_o.mmu_is_store_o                             ),
+    .mmu_dtlb_hit_i             (acc_req_i.mmu_dtlb_hit_i                              ),
+    .mmu_dtlb_ppn_i             (acc_req_i.mmu_dtlb_ppn_i                              ),
+    .mmu_valid_i                (acc_req_i.mmu_valid_i                                 ),
+    .mmu_paddr_i                (acc_req_i.mmu_paddr_i                                 ),
+    .mmu_exception_i            (acc_req_i.mmu_exception_i                             ),
     // Load unit
     .ldu_result_req_o           (ldu_result_req                                        ),
     .ldu_result_addr_o          (ldu_result_addr                                       ),

diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
@@ -21,8 +21,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
     input  logic                                 clk_i,
     input  logic                                 rst_ni,
     // Interfaces with Ariane
-    input  accelerator_req_t                     acc_req_i,
-    output accelerator_resp_t                    acc_resp_o,
+    input  cva6_to_acc_t                         acc_req_i,
+    output acc_to_cva6_t                         acc_resp_o,
     // Interface with Ara's backend
     output ara_req_t                             ara_req_o,
     output logic                                 ara_req_valid_o,

diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv
@@ -73,12 +73,12 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
   //  Ara and Ariane  //
   //////////////////////
 
-  import acc_pkg::accelerator_req_t;
-  import acc_pkg::accelerator_resp_t;
+  import acc_pkg::cva6_to_acc_t;
+  import acc_pkg::acc_to_cva6_t;
 
   // Accelerator ports
-  accelerator_req_t                     acc_req;
-  accelerator_resp_t                    acc_resp;
+  cva6_to_acc_t                         acc_req;
+  acc_to_cva6_t                         acc_resp;
   logic                                 acc_resp_valid;
   logic                                 acc_resp_ready;
   logic                                 acc_cons_en;
@@ -113,8 +113,8 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
 `else
   cva6 #(
     .CVA6Cfg          (CVA6Cfg                    ),
-    .cvxif_req_t      (acc_pkg::accelerator_req_t ),
-    .cvxif_resp_t     (acc_pkg::accelerator_resp_t),
+    .cvxif_req_t      (acc_pkg::cva6_to_acc_t     ),
+    .cvxif_resp_t     (acc_pkg::acc_to_cva6_t     ),
     .axi_ar_chan_t    (ariane_axi_ar_t            ),
     .axi_aw_chan_t    (ariane_axi_aw_t            ),
     .axi_w_chan_t     (ariane_axi_w_t             ),