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[hardware] Adapt parametrization to pulp-v2 CVA6
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@mp-17
mp-17 committed Nov 11, 2024
1 parent f156705 commit 4156176
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Showing 11 changed files with 252 additions and 141 deletions.
8 changes: 1 addition & 7 deletions hardware/include/ara_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -293,13 +293,7 @@ package ara_pkg;
// Accelerator interface //
/////////////////////////////

// Use Ariane's accelerator interface.
typedef acc_pkg::cva6_to_acc_t cva6_to_acc_t;
typedef acc_pkg::acc_to_cva6_t acc_to_cva6_t;
typedef acc_pkg::accelerator_req_t accelerator_req_t;
typedef acc_pkg::accelerator_resp_t accelerator_resp_t;
typedef acc_pkg::acc_mmu_req_t acc_mmu_req_t;
typedef acc_pkg::acc_mmu_resp_t acc_mmu_resp_t;
// See CVA6 and Ara main modules

////////////////////
// PE interface //
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13 changes: 9 additions & 4 deletions hardware/src/accel_dispatcher_ideal.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,12 @@
`define N_VINSN 1
`endif

module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (
module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; # (
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
parameter type accelerator_req_t = logic,
parameter type accelerator_resp_t = logic,
localparam type xlen_t = logic [CVA6Cfg.XLEN-1:0]
) (
input logic clk_i,
input logic rst_ni,
// Accelerator interaface
Expand All @@ -40,8 +45,8 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (

typedef struct packed {
riscv::instruction_t insn;
riscv::xlen_t rs1;
riscv::xlen_t rs2;
xlen_t rs1;
xlen_t rs2;
} fifo_payload_t;

logic [DATA_WIDTH-1:0] fifo_data_raw;
Expand Down Expand Up @@ -154,7 +159,7 @@ endmodule
typedef struct packed {
riscv::instruction_t insn;
riscv::xlen_t rs1;
xlen_t rs1;
} fifo_payload_t;
fifo_payload_t payload;
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103 changes: 85 additions & 18 deletions hardware/src/ara.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,8 @@ module ara import ara_pkg::*; #(
parameter fpext_support_e FPExtSupport = FPExtSupportEnable,
// Support for fixed-point data types
parameter fixpt_support_e FixPtSupport = FixedPointEnable,
// CVA6 configuration
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
// AXI Interface
parameter int unsigned AxiDataWidth = 0,
parameter int unsigned AxiAddrWidth = 0,
Expand All @@ -32,7 +34,66 @@ module ara import ara_pkg::*; #(
// vector store unit, the slide unit, and the mask unit.
localparam int unsigned NrPEs = NrLanes + 4,
localparam type vlen_t = logic[$clog2(VLEN+1)-1:0],
localparam int unsigned VLENB = VLEN / 8
localparam int unsigned VLENB = VLEN / 8,
// Exception type: should be the same as in CVA6
localparam type exception_t = struct packed {
logic [CVA6Cfg.XLEN-1:0] cause; // cause of exception
logic [CVA6Cfg.XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
logic [CVA6Cfg.GPLEN-1:0] tval2; // additional information when the causing exception in a guest exception
logic [31:0] tinst; // transformed instruction information
logic gva; // signals when a guest virtual address is written to tval
logic valid;
},
// Interfaces (they need the CVA6Cfg)
localparam type acc_mmu_req_t = struct packed {
logic acc_mmu_misaligned_ex;
logic acc_mmu_req;
logic [CVA6Cfg.VLEN-1:0] acc_mmu_vaddr;
logic acc_mmu_is_store;
},
localparam type acc_mmu_resp_t = struct packed {
logic acc_mmu_dtlb_hit;
logic [CVA6Cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
logic acc_mmu_valid;
logic [CVA6Cfg.PLEN-1:0] acc_mmu_paddr;
exception_t acc_mmu_exception;
},
localparam type accelerator_req_t = struct packed {
logic req_valid;
logic resp_ready;
riscv::instruction_t insn;
logic [CVA6Cfg.XLEN-1:0] rs1;
logic [CVA6Cfg.XLEN-1:0] rs2;
fpnew_pkg::roundmode_e frm;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
logic store_pending;
logic acc_cons_en; // Invalidation interface
logic inval_ready; // Invalidation interface
},
localparam type accelerator_resp_t = struct packed {
logic req_ready;
logic resp_valid;
logic [CVA6Cfg.XLEN-1:0] result;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
exception_t exception;
logic store_pending;
logic store_complete;
logic load_complete;
logic [4:0] fflags;
logic fflags_valid;
logic inval_valid; // Invalidation interface
logic [63:0] inval_addr; // Invalidation interface
},
localparam type cva6_to_acc_t = struct packed {
accelerator_req_t acc_req; // Insn/mem
logic acc_mmu_en; // MMU
acc_mmu_resp_t acc_mmu_resp; // MMU
},
localparam type acc_to_cva6_t = struct packed {
accelerator_resp_t acc_resp; // Insn/mem
acc_mmu_req_t acc_mmu_req; // MMU
}
) (
// Clock and Reset
input logic clk_i,
Expand Down Expand Up @@ -145,7 +206,7 @@ module ara import ara_pkg::*; #(
elen_t resp;

// Instruction triggered an exception
ariane_pkg::exception_t exception;
exception_t exception;

// New value for vstart
vlen_t exception_vstart;
Expand Down Expand Up @@ -174,10 +235,13 @@ module ara import ara_pkg::*; #(
vxrm_t [NrLanes-1:0] alu_vxrm;

ara_dispatcher #(
.NrLanes (NrLanes ),
.VLEN (VLEN ),
.ara_req_t (ara_req_t ),
.ara_resp_t(ara_resp_t)
.NrLanes (NrLanes ),
.VLEN (VLEN ),
.CVA6Cfg (CVA6Cfg ),
.ara_req_t (ara_req_t ),
.ara_resp_t (ara_resp_t ),
.accelerator_req_t(accelerator_req_t ),
.accelerator_resp_t(accelerator_resp_t)
) i_dispatcher (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
Expand Down Expand Up @@ -215,7 +279,7 @@ module ara import ara_pkg::*; #(
pe_resp_t [NrPEs-1:0] pe_resp;
// Interface with the address generator
logic addrgen_ack;
ariane_pkg::exception_t addrgen_exception;
exception_t addrgen_exception;
vlen_t addrgen_exception_vstart;
logic [NrLanes-1:0] alu_vinsn_done;
logic [NrLanes-1:0] mfpu_vinsn_done;
Expand All @@ -238,12 +302,13 @@ module ara import ara_pkg::*; #(
logic result_scalar_valid;

ara_sequencer #(
.NrLanes (NrLanes ),
.VLEN (VLEN ),
.ara_req_t (ara_req_t ),
.ara_resp_t(ara_resp_t),
.pe_req_t (pe_req_t ),
.pe_resp_t (pe_resp_t )
.NrLanes (NrLanes ),
.VLEN (VLEN ),
.ara_req_t (ara_req_t ),
.ara_resp_t (ara_resp_t),
.pe_req_t (pe_req_t ),
.pe_resp_t (pe_resp_t ),
.exception_t(exception_t)
) i_sequencer (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
Expand Down Expand Up @@ -413,10 +478,10 @@ module ara import ara_pkg::*; #(

// Optional OS support
logic acc_mmu_misaligned_ex, acc_mmu_req, acc_mmu_is_store, acc_mmu_dtlb_hit, acc_mmu_valid, acc_mmu_en;
logic [riscv::VLEN-1:0] acc_mmu_vaddr;
logic [riscv::PLEN-1:0] acc_mmu_paddr;
logic [riscv::PPNW-1:0] acc_mmu_dtlb_ppn;
ariane_pkg::exception_t acc_mmu_exception;
logic [CVA6Cfg.VLEN-1:0] acc_mmu_vaddr;
logic [CVA6Cfg.PLEN-1:0] acc_mmu_paddr;
logic [CVA6Cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
exception_t acc_mmu_exception;
if (OSSupport) begin
assign acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex = acc_mmu_misaligned_ex;
assign acc_resp_o.acc_mmu_req.acc_mmu_req = acc_mmu_req;
Expand Down Expand Up @@ -455,7 +520,9 @@ module ara import ara_pkg::*; #(
.axi_resp_t (axi_resp_t ),
.vaddr_t (vaddr_t ),
.pe_req_t (pe_req_t ),
.pe_resp_t (pe_resp_t )
.pe_resp_t (pe_resp_t ),
.CVA6Cfg (CVA6Cfg ),
.exception_t (exception_t )
) i_vlsu (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
Expand Down
27 changes: 16 additions & 11 deletions hardware/src/ara_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,15 @@
// response or an error message.

module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
parameter int unsigned NrLanes = 0,
parameter int unsigned VLEN = 0,
parameter type ara_req_t = logic,
parameter type ara_resp_t = logic,
parameter int unsigned NrLanes = 0,
parameter int unsigned VLEN = 0,
parameter type ara_req_t = logic,
parameter type ara_resp_t = logic,
parameter type accelerator_req_t = logic,
parameter type accelerator_resp_t = logic,
// CVA6 configuration
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
localparam type xlen_t = logic [CVA6Cfg.XLEN-1:0],
// Support for floating-point data types
parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble,
// External support for vfrec7, vfrsqrt7
Expand Down Expand Up @@ -71,15 +76,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
`FF(csr_vxsat_q, csr_vxsat_d, '0)
`FF(csr_vxrm_q, csr_vxrm_d, '0)
// Converts between the internal representation of `vtype_t` and the full XLEN-bit CSR.
function automatic riscv::xlen_t xlen_vtype(vtype_t vtype);
xlen_vtype = {vtype.vill, {riscv::XLEN-9{1'b0}}, vtype.vma, vtype.vta, vtype.vsew,
function automatic xlen_t xlen_vtype(vtype_t vtype);
xlen_vtype = {vtype.vill, {CVA6Cfg.XLEN-9{1'b0}}, vtype.vma, vtype.vta, vtype.vsew,
vtype.vlmul[2:0]};
endfunction: xlen_vtype

// Converts between the XLEN-bit vtype CSR and its internal representation
function automatic vtype_t vtype_xlen(riscv::xlen_t xlen);
function automatic vtype_t vtype_xlen(xlen_t xlen);
vtype_xlen = '{
vill : xlen[riscv::XLEN-1],
vill : xlen[CVA6Cfg.XLEN-1],
vma : xlen[7],
vta : xlen[6],
vsew : vew_e'(xlen[5:3]),
Expand Down Expand Up @@ -492,11 +497,11 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(

// Update vtype
if (insn.vsetvli_type.func1 == 1'b0) begin // vsetvli
csr_vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetvli_type.zimm11));
csr_vtype_d = vtype_xlen(xlen_t'(insn.vsetvli_type.zimm11));
end else if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
csr_vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetivli_type.zimm10));
csr_vtype_d = vtype_xlen(xlen_t'(insn.vsetivli_type.zimm10));
end else if (insn.vsetvl_type.func7 == 7'b100_0000) begin // vsetvl
csr_vtype_d = vtype_xlen(riscv::xlen_t'(acc_req_i.rs2[7:0]));
csr_vtype_d = vtype_xlen(xlen_t'(acc_req_i.rs2[7:0]));
end else
illegal_insn = 1'b1;

Expand Down
15 changes: 8 additions & 7 deletions hardware/src/ara_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,13 @@

module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width; #(
// RVV Parameters
parameter int unsigned NrLanes = 1, // Number of parallel vector lanes
parameter int unsigned VLEN = 0,
parameter type ara_req_t = logic,
parameter type ara_resp_t = logic,
parameter type pe_req_t = logic,
parameter type pe_resp_t = logic,
parameter int unsigned NrLanes = 1, // Number of parallel vector lanes
parameter int unsigned VLEN = 0,
parameter type ara_req_t = logic,
parameter type ara_resp_t = logic,
parameter type pe_req_t = logic,
parameter type pe_resp_t = logic,
parameter type exception_t = logic,
// Dependant parameters. DO NOT CHANGE!
// Ara has NrLanes + 3 processing elements: each one of the lanes, the vector load unit, the
// vector store unit, the slide unit, and the mask unit.
Expand Down Expand Up @@ -46,7 +47,7 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
output logic pe_scalar_resp_ready_o,
// Interface with the Address Generation
input logic addrgen_ack_i,
input ariane_pkg::exception_t addrgen_exception_i,
input exception_t addrgen_exception_i,
input vlen_t addrgen_exception_vstart_i
);

Expand Down
93 changes: 29 additions & 64 deletions hardware/src/ara_soc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -444,72 +444,37 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(

assign hart_id = '0;

localparam config_pkg::cva6_cfg_t CVA6AraConfig = '{
NrCommitPorts : 2,
AxiAddrWidth : AxiAddrWidth,
AxiDataWidth : AxiNarrowDataWidth,
AxiIdWidth : AxiIdWidth,
AxiUserWidth : 1,
NrLoadBufEntries : 2,
FpuEn : 1,
XF16 : FPUSupport[0],
XF16ALT : 0,
XF8 : 0,
XF8ALT : 1,
RVA : 1,
RVB : 0,
RVV : 1,
RVC : 1,
RVH : 0,
RVZCB : 0,
XFVec : 0,
CvxifEn : 0,
ZiCondExtEn : 0,
RVSCLIC : 0,
RVF : FPUSupport[1],
RVD : FPUSupport[2],
FpPresent : 1,
NSX : 0,
FLen : 64,
RVFVec : 0,
XF16Vec : 0,
XF16ALTVec : 0,
XF8Vec : 0,
NrRgprPorts : 0,
NrWbPorts : 0,
EnableAccelerator : 1,
RVS : 1,
RVU : 1,
HaltAddress : 64'h800,
ExceptionAddress : 64'h808,
RASDepth : 2,
BTBEntries : 32,
BHTEntries : 128,
DmBaseAddress : 64'h0,
TvalEn : 1,
NrPMPEntries : 0,
PMPCfgRstVal : {16{64'h0}},
PMPAddrRstVal : {16{64'h0}},
PMPEntryReadOnly : 16'd0,
NOCType : config_pkg::NOC_TYPE_AXI4_ATOP,
CLICNumInterruptSrc : 0,
// Modify configuration parameters
function automatic config_pkg::cva6_user_cfg_t gen_usr_cva6_config(config_pkg::cva6_user_cfg_t cfg);
cfg.AxiAddrWidth = AxiAddrWidth;
cfg.AxiDataWidth = AxiNarrowDataWidth;
cfg.AxiIdWidth = AxiIdWidth;
cfg.AxiUserWidth = AxiUserWidth;
cfg.XF16 = FPUSupport[0];
cfg.RVF = FPUSupport[1];
cfg.RVD = FPUSupport[2];
cfg.NrPMPEntries = 0;
cfg.CLICNumInterruptSrc = 0;
// idempotent region
NrNonIdempotentRules : 2,
NonIdempotentAddrBase: {UARTBase, CTRLBase},
NonIdempotentLength : {UARTLength, CTRLLength},
NrExecuteRegionRules : 3,
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: {DRAMBase, 64'h1_0000, 64'h0},
ExecuteRegionLength : {DRAMLength, 64'h10000, 64'h1000},
cfg.NrNonIdempotentRules = 2;
cfg.NonIdempotentAddrBase = {UARTBase, CTRLBase};
cfg.NonIdempotentLength = {UARTLength, CTRLLength};
cfg.NrExecuteRegionRules = 3;
// DRAM; Boot ROM; Debug Module
cfg.ExecuteRegionAddrBase = {DRAMBase, 64'h1_0000, 64'h0};
cfg.ExecuteRegionLength = {DRAMLength, 64'h10000, 64'h1000};
// cached region
NrCachedRegionRules : 1,
CachedRegionAddrBase : {DRAMBase},
CachedRegionLength : {DRAMLength},
MaxOutstandingStores : 7,
DebugEn : 1,
NonIdemPotenceEn : 1,
AxiBurstWriteEn : 0
};
cfg.NrCachedRegionRules = 1;
cfg.CachedRegionAddrBase = {DRAMBase};
cfg.CachedRegionLength = {DRAMLength};
// Return modified config
return cfg;
endfunction

// Generate the user defined package, starting from the template one for RVV
localparam config_pkg::cva6_user_cfg_t CVA6AraConfig_user = gen_usr_cva6_config(cva6_config_pkg::cva6_cfg);
// Build the package
localparam config_pkg::cva6_cfg_t CVA6AraConfig = build_config_pkg::build_config(CVA6AraConfig_user);

`ifndef TARGET_GATESIM
ara_system #(
Expand Down
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