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[hardware] Fix QuestaSim compilation
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mp-17 committed Oct 11, 2024
1 parent 1cfbd76 commit 3dad93d
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Showing 2 changed files with 8 additions and 6 deletions.
4 changes: 0 additions & 4 deletions hardware/include/ara/ara.svh
Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,7 @@
// Structs in ports of hierarchical modules are not supported in Verilator
// --> Flatten them for Verilator
`define STRUCT_PORT_BITS(bits) \
`ifndef VERILATOR \
struct_t \
`else \
logic[bits-1:0] \
`endif

// Create a flattened vector of a struct. Make sure the first dimension is
// the dimension into the vector of struct types and not the struct itself.
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10 changes: 8 additions & 2 deletions hardware/src/lane/lane.sv
Original file line number Diff line number Diff line change
Expand Up @@ -213,6 +213,12 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
logic mfpu_ready;
logic [NrVInsn-1:0] mfpu_vinsn_done;

// Additional signals to please Verilator's hierarchical verilation
pe_req_t pe_req;
pe_resp_t pe_resp;
assign pe_req = pe_req_i;
assign pe_resp_o = pe_resp;

lane_sequencer #(
.NrLanes (NrLanes ),
.pe_req_t (pe_req_t ),
Expand All @@ -224,11 +230,11 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.rst_ni (rst_ni ),
.lane_id_i (lane_id_i ),
// Interface with the main sequencer
.pe_req_i (pe_req_i ),
.pe_req_i (pe_req ),
.pe_req_valid_i (pe_req_valid_i ),
.pe_vinsn_running_i (pe_vinsn_running_i ),
.pe_req_ready_o (pe_req_ready_o ),
.pe_resp_o (pe_resp_o ),
.pe_resp_o (pe_resp ),
// Interface with the operand requesters
.operand_request_o (operand_request ),
.operand_request_valid_o(operand_request_valid),
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