[CHANGELOG] Update Changelog #2599
ci.yml
on: push
tc-llvm
1m 30s
tc-isa-sim
32s
tc-verilator
12s
tc-gcc
51s
check-license
25s
check-trailing-whitespaces
6s
Matrix: compile-apps
check-clang-format
1m 1s
Matrix: compile-ara
Matrix: compile-riscv-tests
Matrix: simulate
Matrix: benchmark
Matrix: riscv-tests-simv
Annotations
5 errors
riscv-tests-simv (2_lanes)
Process completed with exit code 2.
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simulate (fmatmul, 16_lanes)
Canceling since a higher priority waiting request for 'ci-refs/heads/feat/low-prec' exists
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simulate (fmatmul, 16_lanes)
The operation was canceled.
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benchmark (4_lanes)
Canceling since a higher priority waiting request for 'ci-refs/heads/feat/low-prec' exists
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benchmark (4_lanes)
The operation was canceled.
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Artifacts
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dotproducts-2_lanes
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