Add support for Trace Ingress Port (TIP) on CVA6 V5.1.0

[dassheladiya]

Overview

• Adds support for Trace Ingress Port (TIP) on CVA6 V5.1.0

• TIP is Interface between a RISC-V hart and the trace encoder

• It generates information about the instruction retired.

• The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically:

• Chapter 4.1: Instruction Trace Interface Requirements

• Chapter 4.2: Instruction Trace Interface

• The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump.

Changed

• Added new files:
  • core/cva6_tip.sv
  • core/encoder_16_4.sv
• Changes made:
  • core/Flist.cva6 : Added paths.
  • core/cva6.sv : Added TIP and instantiating the cva6_tip block.
  • corev_apu/src/ariane.sv : Added TIP.
  • corev_apu/tb/ariane_testharness.sv : Added TIP for simulation.
• The TIP interface can be enabled or disabled using the IsTIP flag

What I have been able to test so far:

• Simulation: Executed C binaries and observed the waveform of TIP.
• FPGA: A program(in a loop approximately 10 instructions ) was executed on the FPGA, and the output was observed on the Integrated Logic Analyzer (ILA).

What I have not yet tested:

• Did not perform any formal verification.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[JeanRochCoulon]

Hello @dassheladiya Thanks for this nice feature.
First of all, I encourage you to sign-up the Eclipse ECA to be eligible to contribute to OpenHW Group.
In the meantime, the CONTRIBUTING.md contains information to ease the contribution. One is the command to fix the Verible format.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[JeanRochCoulon]

@dassheladiya For reminder, your PR need to be rebase to allow the merge.

[github-actions]

❌ failed run, report available here.

[github-actions]

❌ failed run, report available here.

[github-actions]

✔️ successful run, report available here.

[MikeOpenHWGroup]

Hi @dassheladiya, thank you for this most interesting contribution. I will not be the one to review this pull-request on a technical level, but in order for this contribution to be legal, it must have an appropriate permissive open-source license. We prefer Solderpad2.1, but Apache 2.0 and the EPL are all acceptable.

The technical aspects of adding the license are trivial. For all new files you are contributing, change the header from this:

// Author: Darshak Sheladiya, SYSGO GmbH
// Date: 11/14/2024
// Description: Trace Ingress Port (TIP).

to something like this:

// Copyright (c), 2024 Darshak Sheladiya, SYSGO GmbH
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

Of course, you can also keep the Date and Description comments, this is up to you. You may also include the entire license in the header. Many people do this, but it is not strictly necessary. The SPDX-License-Identifier is both required and sufficient.

The legal aspects of this are important. By adding the above header you are stating many things:

• You are the legal author of this code
• You and SYSGO hold the copyright
• no patents are violated

Please discuss this with your employer to ensure they agree with the above. Again, thank you for this contribution!

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

[github-actions]

✔️ successful run, report available here.

[github-actions]

✔️ successful run, report available here.