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style: use standard code formatting using Verible
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@dassheladiya
dassheladiya committed Nov 14, 2024
1 parent 783ea21 commit d0a9c58
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Showing 3 changed files with 179 additions and 167 deletions.
70 changes: 35 additions & 35 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -35,13 +35,13 @@ module cva6
parameter bit IsTIP = bit'(1),

parameter type tip_instr_t = struct packed {
logic [config_pkg::NRET-1:0] iretire;
logic [config_pkg::NRET*riscv::XLEN-1:0] iaddr; //PC address
logic [config_pkg::NRET*riscv::XLEN-1:0] time_t;
logic [config_pkg::NRET*3-1:0] priv;
logic [config_pkg::NRET*riscv::XLEN-1:0] cause;
logic [config_pkg::NRET*riscv::XLEN-1:0] tval;
logic [config_pkg::NRET*(riscv::XLEN/2)-1:0] itype;
logic [config_pkg::NRET-1:0] iretire;
logic [config_pkg::NRET*riscv::XLEN-1:0] iaddr; //PC address
logic [config_pkg::NRET*riscv::XLEN-1:0] time_t;
logic [config_pkg::NRET*3-1:0] priv;
logic [config_pkg::NRET*riscv::XLEN-1:0] cause;
logic [config_pkg::NRET*riscv::XLEN-1:0] tval;
logic [config_pkg::NRET*(riscv::XLEN/2)-1:0] itype;
},

// branchpredict scoreboard entry
Expand Down Expand Up @@ -1673,34 +1673,34 @@ module cva6
//pragma translate_on


if (IsTIP) begin

//CVA6 Trace Ingress Port
cva6_tip #(
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.scoreboard_entry_t (scoreboard_entry_t),
.rvfi_probes_csr_t (rvfi_probes_csr_t),
.bp_resolve_t(bp_resolve_t),
.tip_instr_t(tip_instr_t),
.rvfi_probes_instr_t(rvfi_probes_instr_t),
.rvfi_probes_t (rvfi_probes_t)
) i_cva6_tip (
.clk_i (clk_i),
.commit_instr_i(commit_instr_id_commit),
.ex_commit_i (ex_commit),
.priv_lvl_i (priv_lvl),
.commit_ack_i(commit_macro_ack),
.debug_mode_i(debug_mode),
.csr_i(rvfi_csr),
.eret_i (eret),
.ipi_i(ipi_i),
.debug_req_i(debug_req_i),
.resolved_branch_i (resolved_branch),
.rvfi_probes_i(rvfi_probes_o),
.tip_o(tip_o)
);
if (IsTIP) begin

//CVA6 Trace Ingress Port
cva6_tip #(
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.scoreboard_entry_t (scoreboard_entry_t),
.rvfi_probes_csr_t (rvfi_probes_csr_t),
.bp_resolve_t (bp_resolve_t),
.tip_instr_t (tip_instr_t),
.rvfi_probes_instr_t(rvfi_probes_instr_t),
.rvfi_probes_t (rvfi_probes_t)
) i_cva6_tip (
.clk_i (clk_i),
.commit_instr_i (commit_instr_id_commit),
.ex_commit_i (ex_commit),
.priv_lvl_i (priv_lvl),
.commit_ack_i (commit_macro_ack),
.debug_mode_i (debug_mode),
.csr_i (rvfi_csr),
.eret_i (eret),
.ipi_i (ipi_i),
.debug_req_i (debug_req_i),
.resolved_branch_i(resolved_branch),
.rvfi_probes_i (rvfi_probes_o),
.tip_o (tip_o)
);

end
end

endmodule // ariane
152 changes: 79 additions & 73 deletions core/cva6_tip.sv
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Original file line number Diff line number Diff line change
@@ -1,3 +1,7 @@
// Author: Darshak Sheladiya, SYSGO GmbH
// Date: 11/14/2024
// Description: Trace Ingress Port (TIP).

module cva6_tip
import ariane_pkg::*;
#(
Expand All @@ -15,8 +19,8 @@ module cva6_tip
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
input exception_t ex_commit_i,
input riscv::priv_lvl_t priv_lvl_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
input logic debug_mode_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
input logic debug_mode_i,
input rvfi_probes_csr_t csr_i,
input logic eret_i,
input logic ipi_i,
Expand All @@ -28,63 +32,65 @@ module cva6_tip



rvfi_probes_instr_t instr= rvfi_probes_i.instr;
logic debug_mode;
rvfi_probes_instr_t instr = rvfi_probes_i.instr;
logic debug_mode;

logic [15:0] itype_signals[0:1];
reg [3:0] itype_o[0:1];
logic [15:0] itype_signals[0:1];
reg [3:0] itype_o[0:1];

riscv::priv_lvl_t priv_lvl;
//debug_mode
assign debug_mode = instr.debug_mode;
assign priv_lvl = instr.priv_lvl;
riscv::priv_lvl_t priv_lvl;
//debug_mode
assign debug_mode = instr.debug_mode;
assign priv_lvl = instr.priv_lvl;


logic [63:0] taken_branch_pc_reg,not_taken_branch_pc_reg,uninforable_jump_pc_reg;
logic [63:0] taken_branch_pc_reg, not_taken_branch_pc_reg, uninforable_jump_pc_reg;

// branch
always@(posedge clk_i) begin
if(resolved_branch_i.cf_type == Branch && resolved_branch_i.is_taken == 1) begin
taken_branch_pc_reg <= resolved_branch_i.pc;// taken branch
end
else if(resolved_branch_i.cf_type == Branch && resolved_branch_i.is_taken == 0)begin
not_taken_branch_pc_reg <= resolved_branch_i.pc; //not taken branch
end
else if(resolved_branch_i.cf_type == JumpR)begin
uninforable_jump_pc_reg <= resolved_branch_i.pc; //JumpR
end
end
// branch
always @(posedge clk_i) begin
if (resolved_branch_i.cf_type == Branch && resolved_branch_i.is_taken == 1) begin
taken_branch_pc_reg <= resolved_branch_i.pc; // taken branch
end else if (resolved_branch_i.cf_type == Branch && resolved_branch_i.is_taken == 0) begin
not_taken_branch_pc_reg <= resolved_branch_i.pc; //not taken branch
end else if (resolved_branch_i.cf_type == JumpR) begin
uninforable_jump_pc_reg <= resolved_branch_i.pc; //JumpR
end
end


// itype signals encoding
generate
for (genvar i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
assign itype_signals [i][1] = commit_instr_i[i].valid && ex_commit_i.valid;
assign itype_signals [i][2] = ( ipi_i || debug_req_i ); //time_irq_i (commit_ack_i[0] && !ex_commit_i.valid) &&
assign itype_signals [i][3] = eret_i;
assign itype_signals [i][4] = ((not_taken_branch_pc_reg == commit_instr_i[i].pc) && ~(commit_instr_i[i].pc == 0));
assign itype_signals [i][5] = ( (taken_branch_pc_reg == commit_instr_i[i].pc) && ~(commit_instr_i[i].pc == 0));
assign itype_signals [i][6] = ( (uninforable_jump_pc_reg == commit_instr_i[i].pc) && ~(commit_instr_i[i].pc == 0));
end
endgenerate
// itype signals encoding
generate
for (genvar i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
assign itype_signals[i][1] = commit_instr_i[i].valid && ex_commit_i.valid;
assign itype_signals [i][2] = ( ipi_i || debug_req_i ); //time_irq_i (commit_ack_i[0] && !ex_commit_i.valid) &&
assign itype_signals[i][3] = eret_i;
assign itype_signals [i][4] = ((not_taken_branch_pc_reg == commit_instr_i[i].pc) && ~(commit_instr_i[i].pc == 0));
assign itype_signals [i][5] = ( (taken_branch_pc_reg == commit_instr_i[i].pc) && ~(commit_instr_i[i].pc == 0));
assign itype_signals [i][6] = ( (uninforable_jump_pc_reg == commit_instr_i[i].pc) && ~(commit_instr_i[i].pc == 0));
end
endgenerate

generate
for (genvar i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
generate
for (genvar i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin

encoder_16_4 ec_0(.in(itype_signals[i]),.out(itype_o[i]),.valid());
encoder_16_4 ec_0 (
.in(itype_signals[i]),
.out(itype_o[i]),
.valid()
);

end
endgenerate
end
endgenerate




//TIP signals
always_comb begin
for (int i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
logic exception, mem_exception;
exception = commit_instr_i[i].valid && ex_commit_i.valid;
mem_exception = exception &&
//TIP signals
always_comb begin
for (int i = 0; i < cva6_config_pkg::CVA6ConfigNrCommitPorts; i++) begin
logic exception, mem_exception;
exception = commit_instr_i[i].valid && ex_commit_i.valid;
mem_exception = exception &&
(ex_commit_i.cause == riscv::INSTR_ADDR_MISALIGNED ||
ex_commit_i.cause == riscv::INSTR_ACCESS_FAULT ||
ex_commit_i.cause == riscv::ILLEGAL_INSTR ||
Expand All @@ -95,45 +101,45 @@ always_comb begin
ex_commit_i.cause == riscv::INSTR_PAGE_FAULT ||
ex_commit_i.cause == riscv::LOAD_PAGE_FAULT ||
ex_commit_i.cause == riscv::STORE_PAGE_FAULT);
tip_o[i].iretire = (commit_ack_i[i] && !ex_commit_i.valid) ||
tip_o[i].iretire = (commit_ack_i[i] && !ex_commit_i.valid) ||
(exception && (ex_commit_i.cause == riscv::ENV_CALL_MMODE ||
ex_commit_i.cause == riscv::ENV_CALL_SMODE ||
ex_commit_i.cause == riscv::ENV_CALL_UMODE));
tip_o[i].iaddr = commit_instr_i[i].pc;
tip_o[i].time_t = csr_i.cycle_q;
tip_o[i].priv = (((CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl) == 2'b10) ? 2'b01:((CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl) ;//(CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;//debug_mode_i ? 3'b100 : priv_lvl_i;
tip_o[i].cause = ex_commit_i.cause;
tip_o[i].tval = csr_i.mtval_q;
tip_o[i].itype = itype_o[i];

end
end
tip_o[i].iaddr = commit_instr_i[i].pc;
tip_o[i].time_t = csr_i.cycle_q;
tip_o[i].priv = (((CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl) == 2'b10) ? 2'b01:((CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl) ;//(CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;//debug_mode_i ? 3'b100 : priv_lvl_i;
tip_o[i].cause = ex_commit_i.cause;
tip_o[i].tval = csr_i.mtval_q;
tip_o[i].itype = itype_o[i];

end
end



//*************************** TIP Signal dumping **************************//
//*************************** TIP Signal dumping **************************//

// int fd = $fopen("./tip_port_0_signals_dump.txt", "w");
// int fj = $fopen("./tip_port_1_signals_dump.txt", "w");
// int fd = $fopen("./tip_port_0_signals_dump.txt", "w");
// int fj = $fopen("./tip_port_1_signals_dump.txt", "w");

// always@(tip_o[0].iretire == 1) begin
// always@(tip_o[0].iretire == 1) begin

// if (fd) begin
// $fwrite(fd, "tip_o_[0].iretire= 0x%h, tip_o_[0].iaddr= 0x%h, tip_o_[0].time_t= 0x%h, tip_o_[0].priv= 0x%h, tip_o_[0].cause= 0x%h, tip_o_[0].tval= 0x%h, tip_o_[0].itype= %h\n", tip_o[0].iretire, tip_o[0].iaddr,tip_o[0].time_t, tip_o[0].priv, tip_o[0].cause, tip_o[0].tval, tip_o[0].itype );
// end else begin
// $display("Error opening the file.");
// end
// end
// if (fd) begin
// $fwrite(fd, "tip_o_[0].iretire= 0x%h, tip_o_[0].iaddr= 0x%h, tip_o_[0].time_t= 0x%h, tip_o_[0].priv= 0x%h, tip_o_[0].cause= 0x%h, tip_o_[0].tval= 0x%h, tip_o_[0].itype= %h\n", tip_o[0].iretire, tip_o[0].iaddr,tip_o[0].time_t, tip_o[0].priv, tip_o[0].cause, tip_o[0].tval, tip_o[0].itype );
// end else begin
// $display("Error opening the file.");
// end
// end

// always@(tip_o[1].iretire == 1) begin
// always@(tip_o[1].iretire == 1) begin

// if (fj) begin
// $fwrite(fj, "tip_o_[1].iretire= 0x%h, tip_o_[1].iaddr= 0x%h, tip_o_[1].time_t= 0x%h, tip_o_[1].priv= 0x%h, tip_o_[1].cause= 0x%h, tip_o_[1].tval= 0x%h, tip_o_[1].itype= %h\n", tip_o[1].iretire, tip_o[1].iaddr,tip_o[1].time_t, tip_o[1].priv, tip_o[1].cause, tip_o[1].tval, tip_o[1].itype );
// end else begin
// $display("Error opening the file.");
// end
// end
// if (fj) begin
// $fwrite(fj, "tip_o_[1].iretire= 0x%h, tip_o_[1].iaddr= 0x%h, tip_o_[1].time_t= 0x%h, tip_o_[1].priv= 0x%h, tip_o_[1].cause= 0x%h, tip_o_[1].tval= 0x%h, tip_o_[1].itype= %h\n", tip_o[1].iretire, tip_o[1].iaddr,tip_o[1].time_t, tip_o[1].priv, tip_o[1].cause, tip_o[1].tval, tip_o[1].itype );
// end else begin
// $display("Error opening the file.");
// end
// end



endmodule
endmodule
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