Parameterization and other fixes for downstream project

Bender.yml

@@ -17,9 +17,11 @@ dependencies:
 frozen: true
 
 sources:
-  - files:
+  - include_dirs:
+      - core/include
+    files:
       - core/include/config_pkg.sv
-
+      - core/include/build_config_pkg.sv
       - target: cv64a6_imafdcv_sv39
         files:
           - core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -107,7 +109,6 @@ sources:
       # Packages
       - core/include/wt_cache_pkg.sv
       - core/include/std_cache_pkg.sv
-      - core/include/acc_pkg.sv
 
       # for all the below files use Flist.cva6 as baseline and also look at Makefile pd/synth
       # CVXIF
@@ -118,11 +119,12 @@ sources:
       - core/cvxif_example/cvxif_example_coprocessor.sv
       - core/cvxif_example/instr_decoder.sv
 
+      - core/cva6_rvfi_probes.sv
+      - core/cva6_fifo_v3.sv
       # vendored deps
       # - include_dirs: [vendor/pulp-platform/common_cells/include/, vendor/pulp-platform/common_cells/src/]
       #   files:
       #     - vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
-      #     - vendor/pulp-platform/common_cells/src/fifo_v3.sv
       #     - vendor/pulp-platform/common_cells/src/lfsr.sv
       #     - vendor/pulp-platform/common_cells/src/lzc.sv
       #     - vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
@@ -244,7 +246,6 @@ sources:
           # Tracer (behavioral code, not RTL)
           - core/include/instr_tracer_pkg.sv
           - common/local/util/instr_tracer.sv
-          - common/local/util/instr_tracer_if.sv
 
     # TODO target define FPGA target + verification etc
     #   - target: test

Flist.ariane

@@ -161,7 +161,6 @@ vendor/openhwgroup/cvfpu/src/fpnew_top.sv
 core/pmp/src/pmp.sv
 core/pmp/src/pmp_entry.sv
 common/local/util/instr_tracer.sv
-common/local/util/instr_tracer_if.sv
 core/cvxif_example/cvxif_example_coprocessor.sv
 core/cvxif_example/instr_decoder.sv
 vendor/pulp-platform/common_cells/src/counter.sv

Makefile

@@ -699,7 +699,6 @@ fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
 fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv)
 fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)
 fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
-fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer_if.sv)
 fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
 fpga_filter += $(addprefix $(root-dir), vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv)
 fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv)

common/local/util/instr_tracer.sv

@@ -22,9 +22,34 @@ module instr_tracer #(
   parameter type bp_resolve_t = logic,
   parameter type scoreboard_entry_t = logic,
   parameter type interrupts_t = logic,
+  parameter type exception_t = logic,
   parameter interrupts_t INTERRUPTS = '0
 )(
-  instr_tracer_if tracer_if,
+    input logic                    pck,
+  input logic                    rstn,
+  input logic                    flush_unissued,
+  input logic                    flush_all,
+  input logic [31:0]             instruction,
+  input logic                    fetch_valid,
+  input logic                    fetch_ack,
+  input logic                    issue_ack, // issue acknowledged
+  input scoreboard_entry_t       issue_sbe, // issue scoreboard entry
+  input logic [1:0][4:0]         waddr, // WB stage
+  input logic [1:0][63:0]        wdata,
+  input logic [1:0]              we_gpr,
+  input logic [1:0]              we_fpr,
+  input scoreboard_entry_t [1:0] commit_instr, // commit instruction
+  input logic [1:0]              commit_ack,
+  input logic                    st_valid,   // stores - address translation
+  input logic [CVA6Cfg.PLEN-1:0] st_paddr,
+  input logic                    ld_valid, // loads
+  input logic                    ld_kill,
+  input logic [CVA6Cfg.PLEN-1:0] ld_paddr,
+  input bp_resolve_t             resolve_branch, // misprediction
+  input exception_t              commit_exception,
+  input riscv::priv_lvl_t        priv_lvl, // current privilege level
+  input logic                    debug_mode,
+
   input logic[CVA6Cfg.XLEN-1:0] hart_id_i
 );
 
@@ -34,7 +59,7 @@ module instr_tracer #(
   logic [31:0] issue_queue [$];
   // issue scoreboard entries
   scoreboard_entry_t issue_sbe_queue [$];
-  scoreboard_entry_t issue_sbe;
+  scoreboard_entry_t issue_sbe_item;
   // store resolved branches, get (mis-)predictions
   bp_resolve_t bp [$];
   // shadow copy of the register files
@@ -69,7 +94,7 @@ module instr_tracer #(
     forever begin
       automatic bp_resolve_t bp_instruction = '0;
       // new cycle, we are only interested if reset is de-asserted
-      @(tracer_if.pck) if (tracer_if.pck.rstn !== 1'b1) begin
+      @(pck) if (rstn !== 1'b1) begin
         flush();
         continue;
       end
@@ -81,94 +106,94 @@ module instr_tracer #(
       // Instruction Decode
       // -------------------
       // we are decoding an instruction
-      if (tracer_if.pck.fetch_valid && tracer_if.pck.fetch_ack) begin
-        decode_instruction = tracer_if.pck.instruction;
+      if (fetch_valid && fetch_ack) begin
+        decode_instruction = instruction;
         decode_queue.push_back(decode_instruction);
       end
       // -------------------
       // Instruction Issue
       // -------------------
       // we got a new issue ack, so put the element from the decode queue to
       // the issue queue
-      if (tracer_if.pck.issue_ack && !tracer_if.pck.flush_unissued) begin
+      if (issue_ack && !flush_unissued) begin
         issue_instruction = decode_queue.pop_front();
         issue_queue.push_back(issue_instruction);
         // also save the scoreboard entry to a separate issue queue
-        issue_sbe_queue.push_back(scoreboard_entry_t'(tracer_if.pck.issue_sbe));
+        issue_sbe_queue.push_back(scoreboard_entry_t'(issue_sbe));
       end
 
       // --------------------
       // Address Translation
       // --------------------
-      if (tracer_if.pck.st_valid) begin
-        store_mapping.push_back(tracer_if.pck.st_paddr);
+      if (st_valid) begin
+        store_mapping.push_back(st_paddr);
       end
 
-      if (tracer_if.pck.ld_valid && !tracer_if.pck.ld_kill) begin
-        load_mapping.push_back(tracer_if.pck.ld_paddr);
+      if (ld_valid && !ld_kill) begin
+        load_mapping.push_back(ld_paddr);
       end
       // ----------------------
       // Store predictions
       // ----------------------
-      if (tracer_if.pck.resolve_branch.valid) begin
-        bp.push_back(tracer_if.pck.resolve_branch);
+      if (resolve_branch.valid) begin
+        bp.push_back(resolve_branch);
       end
       // --------------
       //  Commit
       // --------------
       // we are committing an instruction
       for (int i = 0; i < 2; i++) begin
-        if (tracer_if.pck.commit_ack[i]) begin
-          commit_instruction = scoreboard_entry_t'(tracer_if.pck.commit_instr[i]);
+        if (commit_ack[i]) begin
+          commit_instruction = scoreboard_entry_t'(commit_instr[i]);
           issue_commit_instruction = issue_queue.pop_front();
-          issue_sbe = issue_sbe_queue.pop_front();
+          issue_sbe_item = issue_sbe_queue.pop_front();
           // check if the instruction retiring is a load or store, get the physical address accordingly
-          if (tracer_if.pck.commit_instr[i].fu == ariane_pkg::LOAD)
+          if (commit_instr[i].fu == ariane_pkg::LOAD)
             address_mapping = load_mapping.pop_front();
-          else if (tracer_if.pck.commit_instr[i].fu == ariane_pkg::STORE)
+          else if (commit_instr[i].fu == ariane_pkg::STORE)
             address_mapping = store_mapping.pop_front();
 
-          if (tracer_if.pck.commit_instr[i].fu == ariane_pkg::CTRL_FLOW)
+          if (commit_instr[i].fu == ariane_pkg::CTRL_FLOW)
             bp_instruction = bp.pop_front();
           // the scoreboards issue entry still contains the immediate value as a result
           // check if the write back is valid, if not we need to source the result from the register file
           // as the most recent version of this register will be there.
-          if (tracer_if.pck.we_gpr[i] || tracer_if.pck.we_fpr[i]) begin
-            printInstr(issue_sbe, issue_commit_instruction, tracer_if.pck.wdata[i], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction);
+          if (we_gpr[i] || we_fpr[i]) begin
+            printInstr(issue_sbe_item, issue_commit_instruction, wdata[i], address_mapping, priv_lvl, debug_mode, bp_instruction);
           end else if (ariane_pkg::is_rd_fpr(commit_instruction.op)) begin
-            printInstr(issue_sbe, issue_commit_instruction, fp_reg_file[commit_instruction.rd], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction);
+            printInstr(issue_sbe_item, issue_commit_instruction, fp_reg_file[commit_instruction.rd], address_mapping, priv_lvl, debug_mode, bp_instruction);
           end else begin
-            printInstr(issue_sbe, issue_commit_instruction, gp_reg_file[commit_instruction.rd], address_mapping, tracer_if.pck.priv_lvl, tracer_if.pck.debug_mode, bp_instruction);
+            printInstr(issue_sbe_item, issue_commit_instruction, gp_reg_file[commit_instruction.rd], address_mapping, priv_lvl, debug_mode, bp_instruction);
           end
         end
       end
       // --------------
       // Exceptions
       // --------------
-      if (tracer_if.pck.exception.valid && !(tracer_if.pck.debug_mode && tracer_if.pck.exception.cause == riscv::BREAKPOINT)) begin
+      if (commit_exception.valid && !(debug_mode && commit_exception.cause == riscv::BREAKPOINT)) begin
         // print exception
-        printException(tracer_if.pck.commit_instr[0].pc, tracer_if.pck.exception.cause, tracer_if.pck.exception.tval);
+        printException(commit_instr[0].pc, commit_exception.cause, commit_exception.tval);
       end
       // ----------------------
       // Commit Registers
       // ----------------------
       // update shadow reg files here
       for (int i = 0; i < 2; i++) begin
-        if (tracer_if.pck.we_gpr[i] && tracer_if.pck.waddr[i] != 5'b0) begin
-          gp_reg_file[tracer_if.pck.waddr[i]] = tracer_if.pck.wdata[i];
-        end else if (tracer_if.pck.we_fpr[i]) begin
-          fp_reg_file[tracer_if.pck.waddr[i]] = tracer_if.pck.wdata[i];
+        if (we_gpr[i] && waddr[i] != 5'b0) begin
+          gp_reg_file[waddr[i]] = wdata[i];
+        end else if (we_fpr[i]) begin
+          fp_reg_file[waddr[i]] = wdata[i];
         end
       end
       // --------------
       // Flush Signals
       // --------------
       // flush un-issued instructions
-      if (tracer_if.pck.flush_unissued) begin
+      if (flush_unissued) begin
         flushDecode();
       end
       // flush whole pipeline
-      if (tracer_if.pck.flush) begin
+      if (flush_all) begin
         flush();
       end
     end

core/Flist.cva6

@@ -133,6 +133,7 @@ ${CVA6_REPO_DIR}/core/commit_stage.sv
 ${CVA6_REPO_DIR}/core/axi_shim.sv
 ${CVA6_REPO_DIR}/core/cva6_accel_first_pass_decoder_stub.sv
 ${CVA6_REPO_DIR}/core/acc_dispatcher.sv
+${CVA6_REPO_DIR}/core/cva6_fifo_v3.sv
 
 // What is "frontend"?
 ${CVA6_REPO_DIR}/core/frontend/btb.sv
@@ -178,7 +179,6 @@ ${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
 ${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
 
 // Tracer (behavioral code, not RTL)
-${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
 ${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
 ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv

core/acc_dispatcher.sv

@@ -90,6 +90,7 @@ module acc_dispatcher
     input dcache_req_i_t [2:0] dcache_req_ports_i,
     // Interface with the controller
     output logic ctrl_halt_o,
+    input logic [11:0] csr_addr_i,
     input logic flush_unissued_instr_i,
     input logic flush_ex_i,
     output logic flush_pipeline_o,
@@ -165,7 +166,7 @@ module acc_dispatcher
 
   assign acc_data = acc_valid_ex_o ? fu_data_i : '0;
 
-  fifo_v3 #(
+  cva6_fifo_v3 #(
       .DEPTH       (InstructionQueueDepth),
       .FALL_THROUGH(1'b1),
       .dtype       (fu_data_t),

core/amo_buffer.sv

@@ -62,7 +62,7 @@ module amo_buffer #(
   // e.g.: it is not speculative anymore
   assign flush_amo_buffer = flush_i & !amo_valid_commit_i;
 
-  fifo_v3 #(
+  cva6_fifo_v3 #(
       .DEPTH  (1),
       .dtype  (amo_op_t),
       .FPGA_EN(CVA6Cfg.FpgaEn)

core/cache_subsystem/cache_ctrl.sv

@@ -433,6 +433,9 @@ module cache_ctrl
           state_d = IDLE;
         end
       end
+
+      default:;
+
     endcase
 
     if (req_port_i.kill_req) begin