Parameterization and other fixes for downstream project #1950

zarubaf · 2024-03-21T16:30:53Z

I've encountered some smaller problems when trying to update. Mostly Bender file lists, etc. that shouldn't affect the majority of users here.

Additionally I've fixed some verilator lint warnings as we run a stricter lint deck in-house.

And fifo_v3 needs to be forked since it will clash with the original fifo_v3 from common_cells.

core/acc_dispatcher.sv

github-actions · 2024-03-21T16:31:49Z

core/cache_subsystem/cache_ctrl.sv

@@ -433,6 +433,9 @@ module cache_ctrl
          state_d = IDLE;
        end
      end
+
+      default:;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

default:;

default: ;

github-actions · 2024-03-21T16:31:50Z

core/cache_subsystem/miss_handler.sv

+  logic [31:0] halfword;
+  logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [31:0] halfword;

logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;

logic [ 31:0] halfword;

logic [ $clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;

github-actions · 2024-03-21T16:31:50Z

core/cache_subsystem/miss_handler.sv

+    halfword = '0;
+    cl_offset = '0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

halfword = '0;

cl_offset = '0;

halfword = '0;

cl_offset = '0;

github-actions · 2024-03-21T16:31:50Z

core/cache_subsystem/miss_handler.sv

@@ -491,6 +495,8 @@
          end
        end
      end
+
+      default:;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

default:;

default: ;

github-actions · 2024-03-21T16:31:51Z

core/cva6_fifo_v3.sv

+// pragma translate_off
+`ifndef VERILATOR
+    initial begin
+        assert (DEPTH > 0)             else $error("DEPTH must be greater than 0.");


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// pragma translate_off

`ifndef VERILATOR

initial begin

assert (DEPTH > 0) else $error("DEPTH must be greater than 0.");

// FIFO is in pass through mode -> do not change the pointers

if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin

data_o = data_i;

if (pop_i) begin

status_cnt_n = status_cnt_q;

read_pointer_n = read_pointer_q;

write_pointer_n = write_pointer_q;

end

github-actions · 2024-03-21T16:31:51Z

core/cva6_fifo_v3.sv

+    initial begin
+        assert (DEPTH > 0)             else $error("DEPTH must be greater than 0.");
+    end
+


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

// sequential process

always_ff @(posedge clk_i or negedge rst_ni) begin

if (~rst_ni) begin

read_pointer_q <= '0;

write_pointer_q <= '0;

status_cnt_q <= '0;

end else begin

if (flush_i) begin

read_pointer_q <= '0;

write_pointer_q <= '0;

status_cnt_q <= '0;

end else begin

read_pointer_q <= read_pointer_n;

write_pointer_q <= write_pointer_n;

status_cnt_q <= status_cnt_n;

end

end

end

if (FPGA_EN) begin : gen_fpga_queue

AsyncDpRam #(

.ADDR_WIDTH(ADDR_DEPTH),

.DATA_DEPTH(DEPTH),

.DATA_WIDTH($bits(dtype))

) fifo_ram (

.Clk_CI (clk_i),

.WrEn_SI (fifo_ram_we),

.RdAddr_DI(fifo_ram_read_address),

.WrAddr_DI(fifo_ram_write_address),

.WrData_DI(fifo_ram_wdata),

.RdData_DO(fifo_ram_rdata)

);

end else begin : gen_asic_queue

always_ff @(posedge clk_i or negedge rst_ni) begin

if (~rst_ni) begin

mem_q <= '0;

end else if (!gate_clock) begin

mem_q <= mem_n;

end

end

end

github-actions · 2024-03-21T16:31:51Z

core/cva6_fifo_v3.sv

+    full_write : assert property(
+        @(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))
+        else $fatal (1, "Trying to push new data although the FIFO is full.");
+
+    empty_read : assert property(
+        @(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
+        else $fatal (1, "Trying to pop data although the FIFO is empty.");


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

full_write : assert property(

@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))

else $fatal (1, "Trying to push new data although the FIFO is full.");

empty_read : assert property(

@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))

else $fatal (1, "Trying to pop data although the FIFO is empty.");

// pragma translate_off

`ifndef VERILATOR

initial begin

assert (DEPTH > 0)

else $error("DEPTH must be greater than 0.");

end

full_write :

assert property (@(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i))

else $fatal(1, "Trying to push new data although the FIFO is full.");

empty_read :

assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))

else $fatal(1, "Trying to pop data although the FIFO is empty.");

github-actions · 2024-03-21T16:31:51Z

core/cva6_fifo_v3.sv

+        @(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
+        else $fatal (1, "Trying to pop data although the FIFO is empty.");
+`endif
+// pragma translate_on


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// pragma translate_on

// pragma translate_on

github-actions · 2024-03-21T16:31:51Z

core/cva6_fifo_v3.sv

+`endif
+// pragma translate_on
+
+endmodule // fifo_v3


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endmodule // fifo_v3

endmodule // fifo_v3

github-actions · 2024-03-21T16:36:00Z

❌ failed run, report available here.

github-actions · 2024-03-21T17:30:52Z

✔️ successful run, report available here.

github-actions · 2024-03-21T18:31:17Z

✔️ successful run, report available here.

JeanRochCoulon · 2024-03-22T07:26:16Z

To fix the Verible warning, the command is

zarubaf · 2024-03-22T07:39:55Z

To fix the Verible warning, the command is

Do we want to fix this verible issues? And which one do we want to fix? Only data cache?

JeanRochCoulon · 2024-03-22T08:38:12Z

All files contained in cva6/core/ should be fixed by Verible

cathales

Review of parametrization-related things.

core/amo_buffer.sv

core/axi_shim.sv

core/cva6_fifo_v3.sv

core/include/build_config_pkg.sv

core/include/config_pkg.sv

github-actions · 2024-03-25T10:49:24Z

❌ failed run, report available here.

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>

github-actions · 2024-04-04T11:10:16Z

❌ failed run, report available here.

The interface made a bunch of problems with the typedefs so I've removed it.

github-actions · 2024-04-05T09:56:29Z

core/cva6.sv

+      .pck (clk_i),
+      .rstn (rst_ni),
+      .flush_unissued (flush_unissued_instr_ctrl_id),
+      .flush_all (flush_ctrl_ex),
+      .instruction (id_stage_i.fetch_entry_i.instruction),
+      .fetch_valid (id_stage_i.fetch_entry_valid_i),
+      .fetch_ack (id_stage_i.fetch_entry_ready_o),
+      .issue_ack (issue_stage_i.i_scoreboard.issue_ack_i),
+      .issue_sbe (issue_stage_i.i_scoreboard.issue_instr_o),
+      .waddr (waddr_commit_id),
+      .wdata (wdata_commit_id),
+      .we_gpr (we_gpr_commit_id),
+      .we_fpr (we_fpr_commit_id),
+      .commit_instr (commit_instr_id_commit),
+      .commit_ack (commit_ack),
+      .st_valid (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),
+      .st_paddr (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),
+      .ld_valid (ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),
+      .ld_kill (ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),
+      .ld_paddr (ex_stage_i.lsu_i.i_load_unit.paddr_i),
+      .resolve_branch (resolved_branch),
+      .commit_exception (commit_stage_i.exception_o),
+      .priv_lvl (priv_lvl),
+      .debug_mode (debug_mode),
+      .hart_id_i (hart_id_i)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.pck (clk_i),

.rstn (rst_ni),

.flush_unissued (flush_unissued_instr_ctrl_id),

.flush_all (flush_ctrl_ex),

.instruction (id_stage_i.fetch_entry_i.instruction),

.fetch_valid (id_stage_i.fetch_entry_valid_i),

.fetch_ack (id_stage_i.fetch_entry_ready_o),

.issue_ack (issue_stage_i.i_scoreboard.issue_ack_i),

.issue_sbe (issue_stage_i.i_scoreboard.issue_instr_o),

.waddr (waddr_commit_id),

.wdata (wdata_commit_id),

.we_gpr (we_gpr_commit_id),

.we_fpr (we_fpr_commit_id),

.commit_instr (commit_instr_id_commit),

.commit_ack (commit_ack),

.st_valid (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),

.st_paddr (ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),

.ld_valid (ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),

.ld_kill (ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),

.ld_paddr (ex_stage_i.lsu_i.i_load_unit.paddr_i),

.resolve_branch (resolved_branch),

.commit_exception (commit_stage_i.exception_o),

.priv_lvl (priv_lvl),

.debug_mode (debug_mode),

.hart_id_i (hart_id_i)

.pck(clk_i),

.rstn(rst_ni),

.flush_unissued(flush_unissued_instr_ctrl_id),

.flush_all(flush_ctrl_ex),

.instruction(id_stage_i.fetch_entry_i.instruction),

.fetch_valid(id_stage_i.fetch_entry_valid_i),

.fetch_ack(id_stage_i.fetch_entry_ready_o),

.issue_ack(issue_stage_i.i_scoreboard.issue_ack_i),

.issue_sbe(issue_stage_i.i_scoreboard.issue_instr_o),

.waddr(waddr_commit_id),

.wdata(wdata_commit_id),

.we_gpr(we_gpr_commit_id),

.we_fpr(we_fpr_commit_id),

.commit_instr(commit_instr_id_commit),

.commit_ack(commit_ack),

.st_valid(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.valid_i),

.st_paddr(ex_stage_i.lsu_i.i_store_unit.store_buffer_i.paddr_i),

.ld_valid(ex_stage_i.lsu_i.i_load_unit.req_port_o.tag_valid),

.ld_kill(ex_stage_i.lsu_i.i_load_unit.req_port_o.kill_req),

.ld_paddr(ex_stage_i.lsu_i.i_load_unit.paddr_i),

.resolve_branch(resolved_branch),

.commit_exception(commit_stage_i.exception_o),

.priv_lvl(priv_lvl),

.debug_mode(debug_mode),

.hart_id_i(hart_id_i)

zarubaf · 2024-04-05T09:57:30Z

There are two other fixes that were needed for questa to understand the nested typedef structs. They are sometimes not that well supported.

/cc @domenicw

github-actions · 2024-04-05T10:47:47Z

✔️ successful run, report available here.

zarubaf requested a review from JeanRochCoulon as a code owner March 21, 2024 16:30

zarubaf requested a review from cathales March 21, 2024 16:31

github-actions bot reviewed Mar 21, 2024

View reviewed changes

cathales suggested changes Mar 25, 2024

View reviewed changes

core/amo_buffer.sv Show resolved Hide resolved

core/axi_shim.sv Outdated Show resolved Hide resolved

core/cva6_fifo_v3.sv Show resolved Hide resolved

core/include/build_config_pkg.sv Show resolved Hide resolved

core/include/config_pkg.sv Show resolved Hide resolved

zarubaf and others added 9 commits April 4, 2024 09:49

Bender fixes and switch to cva6_fifo_v3

b6979c0

cfg: Fix verilator warnings

87061f9

Bender: Fix yml

2618789

acc_dispatcher: Add csr_addr_i

7694781

parameterization: Fox AXI_USER_EN warning

3603b8e

wb_cache: Fix Verilator Lint warnings

01a8cc1

cva6_fifo_v3: Add to Flist

bb7e521

Update core/acc_dispatcher.sv

9f8e6d8

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>

parameterization: Address review concerns

1fab902

zarubaf force-pushed the zarubaf/fix-integration branch from ba35588 to 1fab902 Compare April 4, 2024 10:56

zarubaf added 2 commits April 4, 2024 11:33

Switch to cva6_fifo_v3

471cd8b

tracer: Remove tracer interface

2efd720

The interface made a bunch of problems with the typedefs so I've removed it.

github-actions bot reviewed Apr 5, 2024

View reviewed changes

zarubaf merged commit 38e8c05 into master Apr 5, 2024
10 checks passed

zarubaf deleted the zarubaf/fix-integration branch April 5, 2024 11:02

JeanRochCoulon mentioned this pull request Apr 8, 2024

[HOT FIX] Verible reformat #2014

Merged

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Parameterization and other fixes for downstream project #1950

Parameterization and other fixes for downstream project #1950

zarubaf commented Mar 21, 2024 •

edited

Loading

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot Mar 21, 2024

github-actions bot commented Mar 21, 2024

github-actions bot commented Mar 21, 2024

github-actions bot commented Mar 21, 2024

JeanRochCoulon commented Mar 22, 2024

zarubaf commented Mar 22, 2024

JeanRochCoulon commented Mar 22, 2024

cathales left a comment

github-actions bot commented Mar 25, 2024

github-actions bot commented Apr 4, 2024

github-actions bot Apr 5, 2024

zarubaf commented Apr 5, 2024

github-actions bot commented Apr 5, 2024

		logic [31:0] halfword;
		logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;

-// pragma translate_off
-`ifndef VERILATOR
-    initial begin
-        assert (DEPTH > 0)             else $error("DEPTH must be greater than 0.");
+    // FIFO is in pass through mode -> do not change the pointers
+    if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin
+      data_o = data_i;
+      if (pop_i) begin
+        status_cnt_n = status_cnt_q;
+        read_pointer_n = read_pointer_q;
+        write_pointer_n = write_pointer_q;
+      end

+  end
+  // sequential process
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (~rst_ni) begin
+      read_pointer_q  <= '0;
+      write_pointer_q <= '0;
+      status_cnt_q    <= '0;
+    end else begin
+      if (flush_i) begin
+        read_pointer_q  <= '0;
+        write_pointer_q <= '0;
+        status_cnt_q    <= '0;
+      end else begin
+        read_pointer_q  <= read_pointer_n;
+        write_pointer_q <= write_pointer_n;
+        status_cnt_q    <= status_cnt_n;
+      end
+    end
+  end
+  if (FPGA_EN) begin : gen_fpga_queue
+    AsyncDpRam #(
+        .ADDR_WIDTH(ADDR_DEPTH),
+        .DATA_DEPTH(DEPTH),
+        .DATA_WIDTH($bits(dtype))
+    ) fifo_ram (
+        .Clk_CI   (clk_i),
+        .WrEn_SI  (fifo_ram_we),
+        .RdAddr_DI(fifo_ram_read_address),
+        .WrAddr_DI(fifo_ram_write_address),
+        .WrData_DI(fifo_ram_wdata),
+        .RdData_DO(fifo_ram_rdata)
+    );
+  end else begin : gen_asic_queue
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (~rst_ni) begin
+        mem_q <= '0;
+      end else if (!gate_clock) begin
+        mem_q <= mem_n;
+      end
+    end
+  end

Parameterization and other fixes for downstream project #1950

Parameterization and other fixes for downstream project #1950

Conversation

zarubaf commented Mar 21, 2024 • edited Loading

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot Mar 21, 2024

Choose a reason for hiding this comment

github-actions bot commented Mar 21, 2024

github-actions bot commented Mar 21, 2024

github-actions bot commented Mar 21, 2024

JeanRochCoulon commented Mar 22, 2024

zarubaf commented Mar 22, 2024

JeanRochCoulon commented Mar 22, 2024

cathales left a comment

Choose a reason for hiding this comment

github-actions bot commented Mar 25, 2024

github-actions bot commented Apr 4, 2024

github-actions bot Apr 5, 2024

Choose a reason for hiding this comment

zarubaf commented Apr 5, 2024

github-actions bot commented Apr 5, 2024

zarubaf commented Mar 21, 2024 •

edited

Loading