Parametrization step 3 part 1 #1935

cathales · 2024-03-15T16:31:14Z

This PR moves values out of packages so that they can be configured by the configuration structure.

This is the third step for #1451. Many values are moved but not all values are moved yet (do not close the issue).

See also the announcement on Mattermost

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-03-15T16:32:01Z

core/acc_dispatcher.sv

@@ -30,7 +30,7 @@ module acc_dispatcher
      logic [riscv::XLEN-1:0]               rs1;
      logic [riscv::XLEN-1:0]               rs2;
      fpnew_pkg::roundmode_e                frm;
-      logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
+      logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
      logic                                 store_pending;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic store_pending;

logic store_pending;

github-actions · 2024-03-15T16:32:01Z

core/acc_dispatcher.sv

      logic                                 req_ready;
      logic                                 resp_valid;
      logic [riscv::XLEN-1:0]               result;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic req_ready;

logic resp_valid;

logic [riscv::XLEN-1:0] result;

logic req_ready;

logic resp_valid;

logic [riscv::XLEN-1:0] result;

github-actions · 2024-03-15T16:32:01Z

core/acc_dispatcher.sv

@@ -41,7 +41,7 @@
      logic                                 req_ready;
      logic                                 resp_valid;
      logic [riscv::XLEN-1:0]               result;
-      logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
+      logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
      logic                                 error;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic error;

logic error;

github-actions · 2024-03-15T16:32:01Z

core/cache_subsystem/cache_ctrl.sv


  always_comb begin : way_select
    cl_i = '0;
-    for (int unsigned i = 0; i < DCACHE_SET_ASSOC; i++) if (hit_way_i[i]) cl_i = data_i[i].data;
+    for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) if (hit_way_i[i]) cl_i = data_i[i].data;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) if (hit_way_i[i]) cl_i = data_i[i].data;

for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++)

if (hit_way_i[i]) cl_i = data_i[i].data;

github-actions · 2024-03-15T16:32:01Z

core/cache_subsystem/cva6_hpdcache_subsystem.sv

@@ -520,8 +520,7 @@ module cva6_hpdcache_subsystem
  //  AXI arbiter instantiation
  //  {{{
  cva6_hpdcache_subsystem_axi_arbiter #(
-      .HPDcacheMemIdWidth   (CVA6Cfg.MEM_TID_WIDTH),
-      .HPDcacheMemDataWidth (CVA6Cfg.AxiDataWidth),
+      .CVA6Cfg(CVA6Cfg),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.CVA6Cfg(CVA6Cfg),

.CVA6Cfg (CVA6Cfg),

github-actions · 2024-03-15T16:32:03Z

core/cache_subsystem/tag_cmp.sv

    output logic    [      ADDR_WIDTH-1:0] addr_o,
    output l_data_t                        wdata_o,
    output logic                           we_o,
    output l_be_t                          be_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [ ADDR_WIDTH-1:0] addr_o,

output l_data_t wdata_o,

output logic we_o,

output l_be_t be_o,

output logic [ ADDR_WIDTH-1:0] addr_o,

output l_data_t wdata_o,

output logic we_o,

output l_be_t be_o,

github-actions · 2024-03-15T16:32:03Z

core/cache_subsystem/wt_cache_subsystem.sv

+    logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] idx;  // physical address to invalidate
+    logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0]                  way;  // way to invalidate


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate

logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] way; // way to invalidate

logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate

logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] way; // way to invalidate

github-actions · 2024-03-15T16:32:03Z

core/cache_subsystem/wt_dcache.sv

  logic                                                             wr_cl_vld;
  logic                                                             wr_cl_nc;
-  logic     [      DCACHE_SET_ASSOC-1:0]                            wr_cl_we;
-  logic     [      DCACHE_TAG_WIDTH-1:0]                            wr_cl_tag;
+  logic     [      CVA6Cfg.DCACHE_SET_ASSOC-1:0]                            wr_cl_we;
+  logic     [      CVA6Cfg.DCACHE_TAG_WIDTH-1:0]                            wr_cl_tag;
  logic     [   DCACHE_CL_IDX_WIDTH-1:0]                            wr_cl_idx;
-  logic     [   DCACHE_OFFSET_WIDTH-1:0]                            wr_cl_off;
-  logic     [     DCACHE_LINE_WIDTH-1:0]                            wr_cl_data;
-  logic     [DCACHE_USER_LINE_WIDTH-1:0]                            wr_cl_user;
-  logic     [   DCACHE_LINE_WIDTH/8-1:0]                            wr_cl_data_be;
-  logic     [      DCACHE_SET_ASSOC-1:0]                            wr_vld_bits;
-  logic     [      DCACHE_SET_ASSOC-1:0]                            wr_req;
+  logic     [   CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0]                            wr_cl_off;
+  logic     [     CVA6Cfg.DCACHE_LINE_WIDTH-1:0]                            wr_cl_data;
+  logic     [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0]                            wr_cl_user;
+  logic     [   CVA6Cfg.DCACHE_LINE_WIDTH/8-1:0]                            wr_cl_data_be;
+  logic     [      CVA6Cfg.DCACHE_SET_ASSOC-1:0]                            wr_vld_bits;
+  logic     [      CVA6Cfg.DCACHE_SET_ASSOC-1:0]                            wr_req;
  logic                                                             wr_ack;
  logic     [   DCACHE_CL_IDX_WIDTH-1:0]                            wr_idx;
-  logic     [   DCACHE_OFFSET_WIDTH-1:0]                            wr_off;
+  logic     [   CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0]                            wr_off;
  logic     [           riscv::XLEN-1:0]                            wr_data;
  logic     [       (riscv::XLEN/8)-1:0]                            wr_data_be;
-  logic     [     DCACHE_USER_WIDTH-1:0]                            wr_user;
+  logic     [     CVA6Cfg.DCACHE_USER_WIDTH-1:0]                            wr_user;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

logic wr_cl_vld;

logic wr_cl_nc;

logic [ DCACHE_SET_ASSOC-1:0] wr_cl_we;

logic [ DCACHE_TAG_WIDTH-1:0] wr_cl_tag;

logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_cl_we;

logic [ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] wr_cl_tag;

logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx;

logic [ DCACHE_OFFSET_WIDTH-1:0] wr_cl_off;

logic [ DCACHE_LINE_WIDTH-1:0] wr_cl_data;

logic [DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user;

logic [ DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be;

logic [ DCACHE_SET_ASSOC-1:0] wr_vld_bits;

logic [ DCACHE_SET_ASSOC-1:0] wr_req;

logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_cl_off;

logic [ CVA6Cfg.DCACHE_LINE_WIDTH-1:0] wr_cl_data;

logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user;

logic [ CVA6Cfg.DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be;

logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_vld_bits;

logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_req;

logic wr_ack;

logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx;

logic [ DCACHE_OFFSET_WIDTH-1:0] wr_off;

logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off;

logic [ riscv::XLEN-1:0] wr_data;

logic [ (riscv::XLEN/8)-1:0] wr_data_be;

logic [ DCACHE_USER_WIDTH-1:0] wr_user;

logic [ CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user;

logic wr_cl_vld;

logic wr_cl_nc;

logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_cl_we;

logic [ CVA6Cfg.DCACHE_TAG_WIDTH-1:0] wr_cl_tag;

logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_cl_idx;

logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_cl_off;

logic [ CVA6Cfg.DCACHE_LINE_WIDTH-1:0] wr_cl_data;

logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] wr_cl_user;

logic [ CVA6Cfg.DCACHE_LINE_WIDTH/8-1:0] wr_cl_data_be;

logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_vld_bits;

logic [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] wr_req;

logic wr_ack;

logic [ DCACHE_CL_IDX_WIDTH-1:0] wr_idx;

logic [ CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] wr_off;

logic [ riscv::XLEN-1:0] wr_data;

logic [ (riscv::XLEN/8)-1:0] wr_data_be;

logic [ CVA6Cfg.DCACHE_USER_WIDTH-1:0] wr_user;

github-actions · 2024-03-15T16:32:03Z

core/cache_subsystem/wt_dcache.sv

@@ -318,6 +323,7 @@

  wt_dcache_mem #(
      .CVA6Cfg  (CVA6Cfg),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.CVA6Cfg (CVA6Cfg),

.CVA6Cfg(CVA6Cfg),

github-actions · 2024-03-15T16:32:03Z

core/cache_subsystem/wt_dcache.sv

@@ -318,6 +323,7 @@

  wt_dcache_mem #(
      .CVA6Cfg  (CVA6Cfg),
+      .DCACHE_CL_IDX_WIDTH(DCACHE_CL_IDX_WIDTH),
      .wbuffer_t(wbuffer_t),
      .NumPorts (NumPorts)


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.NumPorts (NumPorts)

.NumPorts(NumPorts)

github-actions · 2024-03-15T17:18:36Z

✔️ successful run, report available here.

cathales added 30 commits March 15, 2024 15:28

move NR_SB_ENTRIES & TRANS_ID_BITS

1450510

remove default rvfi_instr_t from spike.sv

a45fc92

fifo_v3: ariane_pkg::FPGA_EN becomes a param

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move FPGA_EN

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inline wt_cache_pkg::L15_SET_ASSOC

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move wt_cache_pkg::L15_WAY_WIDTH

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inline wt_cache_pkg::L1I_SET_ASSOC

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inline wt_cache_pkg::L1D_SET_ASSOC

bdf7bab

move wt_cache_pkg::DCACHE_CL_IDX_WIDTH

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move ICACHE_TAG_WIDTH

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move DCACHE_TAG_WIDTH

9d2aadd

move ICACHE_INDEX_WIDTH

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move ICACHE_SET_ASSOC

b60fafa

use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)

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move DCACHE_NUM_WORDS

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move DCACHE_INDEX_WIDTH

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move DCACHE_OFFSET_WIDTH

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move DCACHE_BYTE_OFFSET

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move DCACHE_DIRTY_WIDTH

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move DCACHE_SET_ASSOC_WIDTH

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move DCACHE_SET_ASSOC

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move CONFIG_L1I_SIZE

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move CONFIG_L1D_SIZE

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move DCACHE_LINE_WIDTH

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move ICACHE_LINE_WIDTH

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move ICACHE_USER_LINE_WIDTH

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move DCACHE_USER_LINE_WIDTH

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DATA_USER_WIDTH = DCACHE_USER_WIDTH

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move DCACHE_USER_WIDTH

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move FETCH_USER_WIDTH

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cathales added 15 commits March 15, 2024 15:28

move FETCH_USER_EN

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move LOG2_INSTR_PER_FETCH

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move INSTR_PER_FETCH

e4f29c6

move FETCH_WIDTH

68bf13d

transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions

3bda6b5

move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure

67b541b

move SV

2816261

move vm_mode_t to config_pkg

bfd10c1

move MODE_SV

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move VPN2

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move PPNW

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move ASIDW

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move ModeW

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move XLEN_ALIGN_BYTES

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move DATA_USER_EN

87b6247

cathales requested review from JeanRochCoulon and zarubaf as code owners March 15, 2024 16:31

github-actions bot reviewed Mar 15, 2024

View reviewed changes

format: apply verible

95e0714

ASintzoff merged commit 987c645 into openhwgroup:master Mar 15, 2024
6 checks passed

cathales deleted the parametrization branch March 15, 2024 17:23

cathales changed the title ~~Parametrization step 3~~ Parametrization step 3 part 1 Mar 15, 2024

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Parametrization step 3 part 1 #1935

Parametrization step 3 part 1 #1935

cathales commented Mar 15, 2024

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github-actions bot commented Mar 15, 2024

	for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) if (hit_way_i[i]) cl_i = data_i[i].data;
	for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++)
	if (hit_way_i[i]) cl_i = data_i[i].data;

		logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate
		logic [CVA6Cfg.DCACHE_SET_ASSOC_WIDTH-1:0] way; // way to invalidate

Parametrization step 3 part 1 #1935

Parametrization step 3 part 1 #1935

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cathales commented Mar 15, 2024

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