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Mmu unify pr #1929

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1429406
unified mmu
AngelaGonzalezMarino Feb 21, 2024
66875b5
include hypervisor related constants in riscv package
AngelaGonzalezMarino Feb 21, 2024
2d1ef54
change number of TLB entries instantiated in sv39
AngelaGonzalezMarino Feb 21, 2024
288e5b7
modify file list
AngelaGonzalezMarino Feb 21, 2024
b4a4112
instantiate unified mmu in lsu
AngelaGonzalezMarino Feb 21, 2024
05c3632
remove old MMUs
AngelaGonzalezMarino Feb 21, 2024
b1f4009
Apply suggestions from code review
AngelaGonzalezMarino Feb 21, 2024
fae5da5
update file lists with new files of mmu
AngelaGonzalezMarino Feb 21, 2024
7227f18
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Feb 21, 2024
66224fb
TLB entries must be a multiple of 2
AngelaGonzalezMarino Feb 21, 2024
77b8175
Merge branch 'openhwgroup:master' into mmu_unify_pr
AngelaGonzalezMarino Feb 26, 2024
51dac2b
optimize resources
AngelaGonzalezMarino Feb 26, 2024
5562ec8
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Feb 26, 2024
20c59e4
remove default value of ASID_WIDTH
AngelaGonzalezMarino Feb 26, 2024
1be468f
remove unsigned in localparam declaration
AngelaGonzalezMarino Feb 26, 2024
65741ae
remove unsigned in localparam declaration
AngelaGonzalezMarino Feb 26, 2024
e8d1071
remove old comments
AngelaGonzalezMarino Feb 27, 2024
af9ac91
copyright update
AngelaGonzalezMarino Feb 27, 2024
8d445bf
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Feb 27, 2024
de3dcb7
add all copyright lines
AngelaGonzalezMarino Feb 29, 2024
eddd568
fix vcs simulation errors regarding hypervisor extension code
AngelaGonzalezMarino Mar 5, 2024
14d8057
Merge branch 'openhwgroup:master' into mmu_unify_pr
AngelaGonzalezMarino Mar 6, 2024
b6d2859
Merge branch 'openhwgroup:master' into mmu_unify_pr
AngelaGonzalezMarino Mar 6, 2024
b1ed384
make shared TLB optional, by default it is used
AngelaGonzalezMarino Mar 6, 2024
f1eb5de
unified mmu
AngelaGonzalezMarino Feb 21, 2024
9489411
include hypervisor related constants in riscv package
AngelaGonzalezMarino Feb 21, 2024
42717b2
change number of TLB entries instantiated in sv39
AngelaGonzalezMarino Feb 21, 2024
84f885d
modify file list
AngelaGonzalezMarino Feb 21, 2024
2ce026f
instantiate unified mmu in lsu
AngelaGonzalezMarino Feb 21, 2024
a7c6991
remove old MMUs
AngelaGonzalezMarino Feb 21, 2024
145dcec
update file lists with new files of mmu
AngelaGonzalezMarino Feb 21, 2024
0d2fea2
Apply suggestions from code review
AngelaGonzalezMarino Feb 21, 2024
89713e7
TLB entries must be a multiple of 2
AngelaGonzalezMarino Feb 21, 2024
54089ce
optimize resources
AngelaGonzalezMarino Feb 26, 2024
efd8434
remove old comments
AngelaGonzalezMarino Feb 27, 2024
baaa9a4
copyright update
AngelaGonzalezMarino Feb 27, 2024
d14d84e
remove default value of ASID_WIDTH
AngelaGonzalezMarino Feb 26, 2024
b1ce75d
remove unsigned in localparam declaration
AngelaGonzalezMarino Feb 26, 2024
bbd276a
remove unsigned in localparam declaration
AngelaGonzalezMarino Feb 26, 2024
9dbe8d3
add all copyright lines
AngelaGonzalezMarino Feb 29, 2024
a7fcc92
fix vcs simulation errors regarding hypervisor extension code
AngelaGonzalezMarino Mar 5, 2024
32ddc69
Parametrization step 1 (#1896)
cathales Mar 6, 2024
7b014e8
make shared TLB optional, by default it is used
AngelaGonzalezMarino Mar 6, 2024
3f9f8cc
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Mar 14, 2024
a7037b7
Merge branch 'master' into mmu_unify_pr
AngelaGonzalezMarino Mar 14, 2024
eaa47d1
merge parametrization changes into MMU unified
AngelaGonzalezMarino Mar 14, 2024
dd3cc0f
Merge branch 'openhwgroup:master' into mmu_unify_pr
AngelaGonzalezMarino Mar 14, 2024
ec8c6a5
Apply suggestions from code review
AngelaGonzalezMarino Mar 14, 2024
407d3a2
Fix errors reported by VCS
AngelaGonzalezMarino Mar 14, 2024
5557975
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Mar 14, 2024
9d62830
fix vcs reported errors in ranges
AngelaGonzalezMarino Mar 14, 2024
1d7c73e
fix vcs reported errors
AngelaGonzalezMarino Mar 14, 2024
0d3a9b6
fix gitlab-ci
AngelaGonzalezMarino Mar 15, 2024
4f074b6
Merge branch 'master' into mmu_unify_pr
AngelaGonzalezMarino Mar 18, 2024
267b0eb
adapt mmu to parametrization step 3
AngelaGonzalezMarino Mar 18, 2024
0dd9772
Apply suggestions from code review
AngelaGonzalezMarino Mar 18, 2024
8f40a2e
Merge branch 'master' into mmu_unify_pr
AngelaGonzalezMarino Mar 18, 2024
a90b1df
adapt mmu to parametrization step 3 part 2
AngelaGonzalezMarino Mar 18, 2024
b62486e
Merge branch 'master' into mmu_unify_pr
AngelaGonzalezMarino Mar 18, 2024
800af14
Apply suggestions from code review
AngelaGonzalezMarino Mar 18, 2024
22dbe9d
adapt mmu to parametrization step 3 part 3
AngelaGonzalezMarino Mar 18, 2024
2ebe735
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Mar 18, 2024
2a5120a
clean verilator warnings
AngelaGonzalezMarino Mar 19, 2024
a120188
Apply suggestions from code review
AngelaGonzalezMarino Mar 19, 2024
84f9b93
fix verilator warnings in mmu related to exception type
AngelaGonzalezMarino Mar 20, 2024
0dc655d
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Mar 20, 2024
5d4c519
Apply suggestions from code review
AngelaGonzalezMarino Mar 20, 2024
a6ce209
fix shared tlb miss connection
AngelaGonzalezMarino Mar 21, 2024
0123845
Merge branch 'mmu_unify_pr' of github.com:planvtech/cva6 into mmu_uni…
AngelaGonzalezMarino Mar 21, 2024
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42 changes: 24 additions & 18 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -25,59 +25,65 @@ sources:
- core/include/cv64a6_imafdcv_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
- core/mmu_sv39/mmu.sv
- core/mmu_sv39/ptw.sv
- core/cva6_mmu/cva6_tlb.sv
- core/cva6_mmu/cva6_shared_tlb.sv
- core/cva6_mmu/cva6_mmu.sv
- core/cva6_mmu/cva6_ptw.sv
- corev_apu/tb/common/mock_uart.sv

- target: cv64a6_imafdc_sv39
files:
- core/include/cv64a6_imafdc_sv39_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
- core/mmu_sv39/mmu.sv
- core/mmu_sv39/ptw.sv
- core/cva6_mmu/cva6_tlb.sv
- core/cva6_mmu/cva6_shared_tlb.sv
- core/cva6_mmu/cva6_mmu.sv
- core/cva6_mmu/cva6_ptw.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv64a6_imafdc_sv39_wb
files:
- core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv39/tlb.sv
- core/mmu_sv39/mmu.sv
- core/mmu_sv39/ptw.sv
- core/cva6_mmu/cva6_tlb.sv
- core/cva6_mmu/cva6_shared_tlb.sv
- core/cva6_mmu/cva6_mmu.sv
- core/cva6_mmu/cva6_ptw.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv32a6_imac_sv0
files:
- core/include/cv32a6_imac_sv0_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
- core/mmu_sv32/cva6_ptw_sv32.sv
- core/cva6_mmu/cva6_tlb.sv
- core/cva6_mmu/cva6_shared_tlb.sv
- core/cva6_mmu/cva6_mmu.sv
- core/cva6_mmu/cva6_ptw.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv32a6_imac_sv32
files:
- core/include/cv32a6_imac_sv32_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
- core/mmu_sv32/cva6_ptw_sv32.sv
- core/cva6_mmu/cva6_tlb.sv
- core/cva6_mmu/cva6_shared_tlb.sv
- core/cva6_mmu/cva6_mmu.sv
- core/cva6_mmu/cva6_ptw.sv
- core/cva6_accel_first_pass_decoder_stub.sv

- target: cv32a6_imafc_sv32
files:
- core/include/cv32a6_imafc_sv32_config_pkg.sv
- core/include/riscv_pkg.sv
- core/include/ariane_pkg.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
- core/mmu_sv32/cva6_ptw_sv32.sv
- core/cva6_mmu/cva6_tlb.sv
- core/cva6_mmu/cva6_shared_tlb.sv
- core/cva6_mmu/cva6_mmu.sv
- core/cva6_mmu/cva6_ptw.sv
- core/cva6_accel_first_pass_decoder_stub.sv

# included via target core/include/${TARGET_CFG}_config_pkg.sv
Expand Down
7 changes: 4 additions & 3 deletions Flist.ariane
Original file line number Diff line number Diff line change
Expand Up @@ -83,19 +83,20 @@ core/issue_stage.sv
core/load_unit.sv
core/load_store_unit.sv
core/lsu_bypass.sv
core/mmu_sv39/mmu.sv
core/cva6_mmu/cva6_mmu.sv
core/mult.sv
core/multiplier.sv
core/serdiv.sv
core/perf_counters.sv
core/mmu_sv39/ptw.sv
core/cva6_mmu/cva6_ptw.sv
core/ariane_regfile_ff.sv
core/re_name.sv
core/scoreboard.sv
core/store_buffer.sv
core/amo_buffer.sv
core/store_unit.sv
core/mmu_sv39/tlb.sv
core/cva6_mmu/cva6_tlb.sv
core/cva6_mmu/cva6_shared_tlb.sv
core/commit_stage.sv
core/cache_subsystem/wt_dcache_ctrl.sv
core/cache_subsystem/wt_dcache_mem.sv
Expand Down
10 changes: 4 additions & 6 deletions ariane.core
Original file line number Diff line number Diff line change
Expand Up @@ -33,20 +33,18 @@ filesets:
- src/lsu_arbiter.sv
- src/lsu.sv
- src/miss_handler.sv
- src/mmu_sv39/mmu.sv
- src/mmu_sv32/cva6_mmu_sv32.sv
- src/cva6_mmu/cva6_mmu.sv
- src/mult.sv
- src/nbdcache.sv
- src/pcgen_stage.sv
- src/perf_counters.sv
- src/mmu_sv39/ptw.sv
- src/mmu_sv32/cva6_ptw_sv32.sv
- src/cva6_mmu/cva6_ptw.sv
- src/regfile_ff.sv
- src/scoreboard.sv
- src/store_buffer.sv
- src/store_unit.sv
- src/mmu_sv39/tlb.sv
- src/mmu_sv32/cva6_tlb_sv32.sv
- src/cva6_mmu/cva6_tlb.sv
- src/cva6_mmu/cva6_shared_tlb.sv
file_type : systemVerilogSource
depend :
- pulp-platform.org::axi_mem_if
Expand Down
15 changes: 5 additions & 10 deletions core/Flist.cva6
Original file line number Diff line number Diff line change
Expand Up @@ -184,15 +184,10 @@ ${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv

// MMU Sv39
${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
${CVA6_REPO_DIR}/core/mmu_sv39/ptw.sv
${CVA6_REPO_DIR}/core/mmu_sv39/tlb.sv

// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_shared_tlb_sv32.sv
// MMU
${CVA6_REPO_DIR}/core/cva6_mmu/cva6_mmu.sv
${CVA6_REPO_DIR}/core/cva6_mmu/cva6_ptw.sv
${CVA6_REPO_DIR}/core/cva6_mmu/cva6_tlb.sv
${CVA6_REPO_DIR}/core/cva6_mmu/cva6_shared_tlb.sv

// end of manifest
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