Mmu unify pr #1929
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Mmu unify pr #1929
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I am getting an elaboration error with the wrapper:
Do you have the possibility to prepare something like the following structure and check whether the design elaborates with Attached what I've tried so far: |
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@zarubaf Hi, I have been able to compile like this with Questa. Let me know if you can make it too |
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Unfortunately, the two implementations are not equivalent: Some other warnings before: |
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| module cva6_mmu | ||
| import ariane_pkg::*; |
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| import ariane_pkg::*; | |
| import ariane_pkg::*; |
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| parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, | ||
| // parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, //This is the required config param in the hypervisor version for now | ||
| parameter type exception_t = logic, | ||
| parameter type icache_areq_t = logic, | ||
| parameter type icache_arsp_t = logic, | ||
| parameter type icache_dreq_t = logic, | ||
| parameter type icache_drsp_t = logic, | ||
| parameter type dcache_req_i_t = logic, | ||
| parameter type dcache_req_o_t = logic, | ||
| parameter int unsigned INSTR_TLB_ENTRIES = 4, | ||
| parameter int unsigned DATA_TLB_ENTRIES = 4, | ||
| parameter int unsigned SHARED_TLB_DEPTH = 64, | ||
| parameter int unsigned USE_SHARED_TLB = 1, | ||
| parameter int unsigned HYP_EXT = 0, | ||
| parameter int ASID_WIDTH [HYP_EXT:0], | ||
| parameter int unsigned VPN_LEN = 1, | ||
| parameter int unsigned PT_LEVELS = 1 |
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Suggested change
| parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, | |
| // parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, //This is the required config param in the hypervisor version for now | |
| parameter type exception_t = logic, | |
| parameter type icache_areq_t = logic, | |
| parameter type icache_arsp_t = logic, | |
| parameter type icache_dreq_t = logic, | |
| parameter type icache_drsp_t = logic, | |
| parameter type dcache_req_i_t = logic, | |
| parameter type dcache_req_o_t = logic, | |
| parameter int unsigned INSTR_TLB_ENTRIES = 4, | |
| parameter int unsigned DATA_TLB_ENTRIES = 4, | |
| parameter int unsigned SHARED_TLB_DEPTH = 64, | |
| parameter int unsigned USE_SHARED_TLB = 1, | |
| parameter int unsigned HYP_EXT = 0, | |
| parameter int ASID_WIDTH [HYP_EXT:0], | |
| parameter int unsigned VPN_LEN = 1, | |
| parameter int unsigned PT_LEVELS = 1 | |
| parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, | |
| // parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, //This is the required config param in the hypervisor version for now | |
| parameter type exception_t = logic, | |
| parameter type icache_areq_t = logic, | |
| parameter type icache_arsp_t = logic, | |
| parameter type icache_dreq_t = logic, | |
| parameter type icache_drsp_t = logic, | |
| parameter type dcache_req_i_t = logic, | |
| parameter type dcache_req_o_t = logic, | |
| parameter int unsigned INSTR_TLB_ENTRIES = 4, | |
| parameter int unsigned DATA_TLB_ENTRIES = 4, | |
| parameter int unsigned SHARED_TLB_DEPTH = 64, | |
| parameter int unsigned USE_SHARED_TLB = 1, | |
| parameter int unsigned HYP_EXT = 0, | |
| parameter int ASID_WIDTH [HYP_EXT:0], | |
| parameter int unsigned VPN_LEN = 1, | |
| parameter int unsigned PT_LEVELS = 1 |
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| pte_cva6_t [ HYP_EXT:0] dtlb_content; | ||
| logic [ PT_LEVELS-2:0] dtlb_is_page; | ||
| logic [ASID_WIDTH[0]-1:0] dtlb_lu_asid; | ||
| logic dtlb_lu_hit; | ||
| logic [ riscv::GPLEN-1:0] dtlb_gpaddr; | ||
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| logic shared_tlb_access,shared_tlb_miss; | ||
| logic shared_tlb_hit, itlb_req; | ||
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| // Assignments | ||
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| assign itlb_lu_access = icache_areq_i.fetch_req; | ||
| assign dtlb_lu_access = lsu_req_i; | ||
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| cva6_tlb #( | ||
| .CVA6Cfg (CVA6Cfg), | ||
| .pte_cva6_t (pte_cva6_t), | ||
| .tlb_update_cva6_t(tlb_update_cva6_t), | ||
| .TLB_ENTRIES (INSTR_TLB_ENTRIES), | ||
| .HYP_EXT (HYP_EXT), | ||
| .ASID_WIDTH (ASID_WIDTH), | ||
| .VPN_LEN (VPN_LEN), | ||
| .PT_LEVELS (PT_LEVELS) | ||
| ) i_itlb ( | ||
| .clk_i (clk_i), | ||
| .rst_ni (rst_ni), | ||
| .flush_i (flush_tlb_i), | ||
| .v_st_enbl_i (enable_translation_i), | ||
| .update_i (update_itlb), | ||
| .lu_access_i (itlb_lu_access), | ||
| .lu_asid_i (itlb_mmu_asid_i), | ||
| .asid_to_be_flushed_i (asid_to_be_flushed_i), | ||
| .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i), | ||
| .lu_vaddr_i (icache_areq_i.fetch_vaddr), | ||
| .lu_content_o (itlb_content), | ||
| .lu_gpaddr_o (itlb_gpaddr), | ||
| .lu_is_page_o (itlb_is_page), | ||
| .lu_hit_o (itlb_lu_hit) | ||
| ); | ||
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| cva6_tlb #( | ||
| .CVA6Cfg (CVA6Cfg), | ||
| .pte_cva6_t (pte_cva6_t), | ||
| .tlb_update_cva6_t(tlb_update_cva6_t), | ||
| .TLB_ENTRIES (DATA_TLB_ENTRIES), | ||
| .HYP_EXT (HYP_EXT), | ||
| .ASID_WIDTH (ASID_WIDTH), | ||
| .VPN_LEN (VPN_LEN), | ||
| .PT_LEVELS (PT_LEVELS) | ||
| ) i_dtlb ( | ||
| .clk_i (clk_i), | ||
| .rst_ni (rst_ni), | ||
| .flush_i (flush_tlb_i), | ||
| .v_st_enbl_i (en_ld_st_translation_i), | ||
| .update_i (update_dtlb), | ||
| .lu_access_i (dtlb_lu_access), | ||
| .lu_asid_i (dtlb_mmu_asid_i), | ||
| .asid_to_be_flushed_i (asid_to_be_flushed_i), | ||
| .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i), | ||
| .lu_vaddr_i (lsu_vaddr_i), | ||
| .lu_content_o (dtlb_content), | ||
| .lu_gpaddr_o (dtlb_gpaddr), | ||
| .lu_is_page_o (dtlb_is_page), | ||
| .lu_hit_o (dtlb_lu_hit) | ||
| ); | ||
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| cva6_shared_tlb #( | ||
| .CVA6Cfg (CVA6Cfg), | ||
| .SHARED_TLB_DEPTH (SHARED_TLB_DEPTH), | ||
| .USE_SHARED_TLB (USE_SHARED_TLB), | ||
| .SHARED_TLB_WAYS (2), | ||
| .HYP_EXT (HYP_EXT), | ||
| .ASID_WIDTH (ASID_WIDTH), | ||
| .VPN_LEN (VPN_LEN), | ||
| .PT_LEVELS (PT_LEVELS), | ||
| .pte_cva6_t (pte_cva6_t), | ||
| .tlb_update_cva6_t(tlb_update_cva6_t) | ||
| ) i_shared_tlb ( | ||
| .clk_i(clk_i), | ||
| .rst_ni(rst_ni), | ||
| .flush_i(flush_tlb_i), | ||
| .v_st_enbl_i({enable_translation_i, en_ld_st_translation_i}), | ||
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| .dtlb_asid_i (dtlb_mmu_asid_i), | ||
| .itlb_asid_i (itlb_mmu_asid_i), | ||
| // from TLBs | ||
| // did we miss? | ||
| .itlb_access_i(itlb_lu_access), | ||
| .itlb_hit_i (itlb_lu_hit), | ||
| .itlb_vaddr_i (icache_areq_i.fetch_vaddr), | ||
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| .dtlb_access_i(dtlb_lu_access), | ||
| .dtlb_hit_i (dtlb_lu_hit), | ||
| .dtlb_vaddr_i (lsu_vaddr_i), | ||
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| // to TLBs, update logic | ||
| .itlb_update_o(update_itlb), | ||
| .dtlb_update_o(update_dtlb), |
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| input logic clk_i, | |
| input logic rst_ni, | |
| input logic flush_i, | |
| input logic [HYP_EXT*2:0] enable_translation_i, //[v_i,enable_g_translation,enable_translation] | |
| input logic [HYP_EXT*2:0] en_ld_st_translation_i, // enable virtual memory translation for ld/st | |
| // IF interface | |
| input icache_arsp_t icache_areq_i, | |
| output icache_areq_t icache_areq_o, | |
| // input icache_areq_o_t icache_areq_i, // this is the data type in the hypervisor version for now | |
| // output icache_areq_i_t icache_areq_o, | |
| // LSU interface | |
| // this is a more minimalistic interface because the actual addressing logic is handled | |
| // in the LSU as we distinguish load and stores, what we do here is simple address translation | |
| input exception_t misaligned_ex_i, | |
| input logic lsu_req_i, // request address translation | |
| input logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_i, // virtual address in | |
| input logic [CVA6Cfg.XLEN-1:0] lsu_tinst_i, // transformed instruction in | |
| input logic lsu_is_store_i, // the translation is requested by a store | |
| output logic csr_hs_ld_st_inst_o, // hyp load store instruction | |
| // if we need to walk the page table we can't grant in the same cycle | |
| // Cycle 0 | |
| output logic lsu_dtlb_hit_o, // sent in same cycle as the request if translation hits in DTLB | |
| output logic [CVA6Cfg.PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit) | |
| // Cycle 1 | |
| output logic lsu_valid_o, // translation is valid | |
| output logic [CVA6Cfg.PLEN-1:0] lsu_paddr_o, // translated address | |
| output exception_t lsu_exception_o, // address translation threw an exception | |
| // General control signals | |
| input riscv::priv_lvl_t priv_lvl_i, | |
| input riscv::priv_lvl_t ld_st_priv_lvl_i, | |
| input logic [HYP_EXT:0] sum_i, | |
| input logic [HYP_EXT:0] mxr_i, | |
| input logic hlvx_inst_i, | |
| input logic hs_ld_st_inst_i, | |
| // input logic flag_mprv_i, | |
| input logic [CVA6Cfg.PPNW-1:0] satp_ppn_i[HYP_EXT*2:0], //[hgatp,vsatp,satp] | |
| input logic [ASID_WIDTH[0]-1:0] asid_i [HYP_EXT*2:0], //[vmid,vs_asid,asid] | |
| input logic [ASID_WIDTH[0]-1:0] asid_to_be_flushed_i [ HYP_EXT:0], | |
| input logic [ CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i[ HYP_EXT:0], | |
| input logic [HYP_EXT*2:0] flush_tlb_i, | |
| // Performance counters | |
| output logic itlb_miss_o, | |
| output logic dtlb_miss_o, | |
| // PTW memory interface | |
| input dcache_req_o_t req_port_i, | |
| output dcache_req_i_t req_port_o, | |
| // PMP | |
| input riscv::pmpcfg_t [15:0] pmpcfg_i, | |
| input logic [15:0][CVA6Cfg.PLEN-3:0] pmpaddr_i | |
| ); | |
| logic [ASID_WIDTH[0]-1:0] dtlb_mmu_asid_i[HYP_EXT:0]; | |
| logic [ASID_WIDTH[0]-1:0] itlb_mmu_asid_i[HYP_EXT:0]; | |
| genvar b; | |
| generate | |
| for (b = 0; b < HYP_EXT + 1; b++) begin : gen_tlbs_asid | |
| assign dtlb_mmu_asid_i[b] = b==0 ? | |
| ((en_ld_st_translation_i[2*HYP_EXT] || flush_tlb_i[HYP_EXT]) ? asid_i[HYP_EXT] : asid_i[0]): | |
| asid_i[HYP_EXT*2]; | |
| assign itlb_mmu_asid_i[b] = b==0 ? | |
| (enable_translation_i[2*HYP_EXT] ? asid_i[HYP_EXT] : asid_i[0]): | |
| asid_i[HYP_EXT*2]; | |
| end | |
| endgenerate | |
| // memory management, pte for cva6 | |
| localparam type pte_cva6_t = struct packed { | |
| logic [CVA6Cfg.PPNW-1:0] ppn; // PPN length for | |
| logic [1:0] rsw; | |
| logic d; | |
| logic a; | |
| logic g; | |
| logic u; | |
| logic x; | |
| logic w; | |
| logic r; | |
| logic v; | |
| }; | |
| localparam type tlb_update_cva6_t = struct packed { | |
| logic valid; | |
| logic [PT_LEVELS-2:0][HYP_EXT:0] is_page; | |
| logic [VPN_LEN-1:0] vpn; | |
| logic [HYP_EXT:0][ASID_WIDTH[0]-1:0] asid; | |
| logic [HYP_EXT*2:0] v_st_enbl; // v_i,g-stage enabled, s-stage enabled | |
| pte_cva6_t [HYP_EXT:0] content; | |
| }; | |
| logic [HYP_EXT:0] iaccess_err; // insufficient privilege to access this instruction page | |
| logic [HYP_EXT:0] daccess_err; // insufficient privilege to access this data page | |
| logic ptw_active; // PTW is currently walking a page table | |
| logic walking_instr; // PTW is walking because of an ITLB miss | |
| logic [HYP_EXT*2:0] ptw_error; // PTW threw an exception | |
| logic ptw_access_exception; // PTW threw an access exception (PMPs) | |
| logic [HYP_EXT:0][CVA6Cfg.PLEN-1:0] ptw_bad_paddr; // PTW guest page fault bad guest physical addr | |
| logic [CVA6Cfg.VLEN-1:0] update_vaddr, shared_tlb_vaddr; | |
| tlb_update_cva6_t update_itlb, update_dtlb, update_shared_tlb; | |
| logic itlb_lu_access; | |
| pte_cva6_t [ HYP_EXT:0] itlb_content; | |
| logic [ PT_LEVELS-2:0] itlb_is_page; | |
| logic itlb_lu_hit; | |
| logic [ riscv::GPLEN-1:0] itlb_gpaddr; | |
| logic [ASID_WIDTH[0]-1:0] itlb_lu_asid; | |
| logic dtlb_lu_access; | |
| pte_cva6_t [ HYP_EXT:0] dtlb_content; | |
| logic [ PT_LEVELS-2:0] dtlb_is_page; | |
| logic [ASID_WIDTH[0]-1:0] dtlb_lu_asid; | |
| logic dtlb_lu_hit; | |
| logic [ riscv::GPLEN-1:0] dtlb_gpaddr; | |
| logic shared_tlb_access,shared_tlb_miss; | |
| logic shared_tlb_hit, itlb_req; | |
| // Assignments | |
| assign itlb_lu_access = icache_areq_i.fetch_req; | |
| assign dtlb_lu_access = lsu_req_i; | |
| cva6_tlb #( | |
| .CVA6Cfg (CVA6Cfg), | |
| .pte_cva6_t (pte_cva6_t), | |
| .tlb_update_cva6_t(tlb_update_cva6_t), | |
| .TLB_ENTRIES (INSTR_TLB_ENTRIES), | |
| .HYP_EXT (HYP_EXT), | |
| .ASID_WIDTH (ASID_WIDTH), | |
| .VPN_LEN (VPN_LEN), | |
| .PT_LEVELS (PT_LEVELS) | |
| ) i_itlb ( | |
| .clk_i (clk_i), | |
| .rst_ni (rst_ni), | |
| .flush_i (flush_tlb_i), | |
| .v_st_enbl_i (enable_translation_i), | |
| .update_i (update_itlb), | |
| .lu_access_i (itlb_lu_access), | |
| .lu_asid_i (itlb_mmu_asid_i), | |
| .asid_to_be_flushed_i (asid_to_be_flushed_i), | |
| .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i), | |
| .lu_vaddr_i (icache_areq_i.fetch_vaddr), | |
| .lu_content_o (itlb_content), | |
| .lu_gpaddr_o (itlb_gpaddr), | |
| .lu_is_page_o (itlb_is_page), | |
| .lu_hit_o (itlb_lu_hit) | |
| ); | |
| cva6_tlb #( | |
| .CVA6Cfg (CVA6Cfg), | |
| .pte_cva6_t (pte_cva6_t), | |
| .tlb_update_cva6_t(tlb_update_cva6_t), | |
| .TLB_ENTRIES (DATA_TLB_ENTRIES), | |
| .HYP_EXT (HYP_EXT), | |
| .ASID_WIDTH (ASID_WIDTH), | |
| .VPN_LEN (VPN_LEN), | |
| .PT_LEVELS (PT_LEVELS) | |
| ) i_dtlb ( | |
| .clk_i (clk_i), | |
| .rst_ni (rst_ni), | |
| .flush_i (flush_tlb_i), | |
| .v_st_enbl_i (en_ld_st_translation_i), | |
| .update_i (update_dtlb), | |
| .lu_access_i (dtlb_lu_access), | |
| .lu_asid_i (dtlb_mmu_asid_i), | |
| .asid_to_be_flushed_i (asid_to_be_flushed_i), | |
| .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i), | |
| .lu_vaddr_i (lsu_vaddr_i), | |
| .lu_content_o (dtlb_content), | |
| .lu_gpaddr_o (dtlb_gpaddr), | |
| .lu_is_page_o (dtlb_is_page), | |
| .lu_hit_o (dtlb_lu_hit) | |
| ); | |
| cva6_shared_tlb #( | |
| .CVA6Cfg (CVA6Cfg), | |
| .SHARED_TLB_DEPTH (SHARED_TLB_DEPTH), | |
| .USE_SHARED_TLB (USE_SHARED_TLB), | |
| .SHARED_TLB_WAYS (2), | |
| .HYP_EXT (HYP_EXT), | |
| .ASID_WIDTH (ASID_WIDTH), | |
| .VPN_LEN (VPN_LEN), | |
| .PT_LEVELS (PT_LEVELS), | |
| .pte_cva6_t (pte_cva6_t), | |
| .tlb_update_cva6_t(tlb_update_cva6_t) | |
| ) i_shared_tlb ( | |
| .clk_i(clk_i), | |
| .rst_ni(rst_ni), | |
| .flush_i(flush_tlb_i), | |
| .v_st_enbl_i({enable_translation_i, en_ld_st_translation_i}), | |
| .dtlb_asid_i (dtlb_mmu_asid_i), | |
| .itlb_asid_i (itlb_mmu_asid_i), | |
| // from TLBs | |
| // did we miss? | |
| .itlb_access_i(itlb_lu_access), | |
| .itlb_hit_i (itlb_lu_hit), | |
| .itlb_vaddr_i (icache_areq_i.fetch_vaddr), | |
| .dtlb_access_i(dtlb_lu_access), | |
| .dtlb_hit_i (dtlb_lu_hit), | |
| .dtlb_vaddr_i (lsu_vaddr_i), | |
| // to TLBs, update logic | |
| .itlb_update_o(update_itlb), | |
| .dtlb_update_o(update_dtlb), | |
| input logic clk_i, | |
| input logic rst_ni, | |
| input logic flush_i, | |
| input logic [HYP_EXT*2:0] enable_translation_i, //[v_i,enable_g_translation,enable_translation] | |
| input logic [HYP_EXT*2:0] en_ld_st_translation_i, // enable virtual memory translation for ld/st | |
| // IF interface | |
| input icache_arsp_t icache_areq_i, | |
| output icache_areq_t icache_areq_o, | |
| // input icache_areq_o_t icache_areq_i, // this is the data type in the hypervisor version for now | |
| // output icache_areq_i_t icache_areq_o, | |
| // LSU interface | |
| // this is a more minimalistic interface because the actual addressing logic is handled | |
| // in the LSU as we distinguish load and stores, what we do here is simple address translation | |
| input exception_t misaligned_ex_i, | |
| input logic lsu_req_i, // request address translation | |
| input logic [CVA6Cfg.VLEN-1:0] lsu_vaddr_i, // virtual address in | |
| input logic [CVA6Cfg.XLEN-1:0] lsu_tinst_i, // transformed instruction in | |
| input logic lsu_is_store_i, // the translation is requested by a store | |
| output logic csr_hs_ld_st_inst_o, // hyp load store instruction | |
| // if we need to walk the page table we can't grant in the same cycle | |
| // Cycle 0 | |
| output logic lsu_dtlb_hit_o, // sent in same cycle as the request if translation hits in DTLB | |
| output logic [CVA6Cfg.PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit) | |
| // Cycle 1 | |
| output logic lsu_valid_o, // translation is valid | |
| output logic [CVA6Cfg.PLEN-1:0] lsu_paddr_o, // translated address | |
| output exception_t lsu_exception_o, // address translation threw an exception | |
| // General control signals | |
| input riscv::priv_lvl_t priv_lvl_i, | |
| input riscv::priv_lvl_t ld_st_priv_lvl_i, | |
| input logic [HYP_EXT:0] sum_i, | |
| input logic [HYP_EXT:0] mxr_i, | |
| input logic hlvx_inst_i, | |
| input logic hs_ld_st_inst_i, | |
| // input logic flag_mprv_i, | |
| input logic [CVA6Cfg.PPNW-1:0] satp_ppn_i[HYP_EXT*2:0], //[hgatp,vsatp,satp] | |
| input logic [ASID_WIDTH[0]-1:0] asid_i [HYP_EXT*2:0], //[vmid,vs_asid,asid] | |
| input logic [ASID_WIDTH[0]-1:0] asid_to_be_flushed_i [ HYP_EXT:0], | |
| input logic [ CVA6Cfg.VLEN-1:0] vaddr_to_be_flushed_i[ HYP_EXT:0], | |
| input logic [HYP_EXT*2:0] flush_tlb_i, |
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| .itlb_miss_o(itlb_miss_o), | ||
| .dtlb_miss_o(dtlb_miss_o), | ||
| .shared_tlb_miss_i(shared_tlb_miss), | ||
|
|
||
| .shared_tlb_access_o(shared_tlb_access), | ||
| .shared_tlb_hit_o (shared_tlb_hit), | ||
| .shared_tlb_vaddr_o (shared_tlb_vaddr), | ||
|
|
||
| .itlb_req_o (itlb_req), | ||
| // to update shared tlb | ||
| .shared_tlb_update_i(update_shared_tlb) | ||
| ); | ||
|
|
||
| cva6_ptw #( | ||
| .CVA6Cfg (CVA6Cfg), | ||
| // .ArianeCfg ( ArianeCfg ), // this is the configuration needed in the hypervisor extension for now | ||
| .pte_cva6_t (pte_cva6_t), | ||
| .tlb_update_cva6_t(tlb_update_cva6_t), | ||
| .dcache_req_i_t (dcache_req_i_t), | ||
| .dcache_req_o_t (dcache_req_o_t), | ||
| .HYP_EXT (HYP_EXT), | ||
| .ASID_WIDTH (ASID_WIDTH), | ||
| .VPN_LEN (VPN_LEN), | ||
| .PT_LEVELS (PT_LEVELS) | ||
| ) i_ptw ( | ||
| .clk_i (clk_i), | ||
| .rst_ni (rst_ni), | ||
| .flush_i(flush_i), | ||
|
|
||
| .ptw_active_o (ptw_active), | ||
| .walking_instr_o (walking_instr), | ||
| .ptw_error_o (ptw_error), | ||
| .ptw_access_exception_o(ptw_access_exception), | ||
|
|
||
| .enable_translation_i (enable_translation_i), | ||
| .en_ld_st_translation_i(en_ld_st_translation_i), | ||
|
|
||
| .lsu_is_store_i(lsu_is_store_i), |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| .itlb_miss_o(itlb_miss_o), | |
| .dtlb_miss_o(dtlb_miss_o), | |
| .shared_tlb_miss_i(shared_tlb_miss), | |
| .shared_tlb_access_o(shared_tlb_access), | |
| .shared_tlb_hit_o (shared_tlb_hit), | |
| .shared_tlb_vaddr_o (shared_tlb_vaddr), | |
| .itlb_req_o (itlb_req), | |
| // to update shared tlb | |
| .shared_tlb_update_i(update_shared_tlb) | |
| ); | |
| cva6_ptw #( | |
| .CVA6Cfg (CVA6Cfg), | |
| // .ArianeCfg ( ArianeCfg ), // this is the configuration needed in the hypervisor extension for now | |
| .pte_cva6_t (pte_cva6_t), | |
| .tlb_update_cva6_t(tlb_update_cva6_t), | |
| .dcache_req_i_t (dcache_req_i_t), | |
| .dcache_req_o_t (dcache_req_o_t), | |
| .HYP_EXT (HYP_EXT), | |
| .ASID_WIDTH (ASID_WIDTH), | |
| .VPN_LEN (VPN_LEN), | |
| .PT_LEVELS (PT_LEVELS) | |
| ) i_ptw ( | |
| .clk_i (clk_i), | |
| .rst_ni (rst_ni), | |
| .flush_i(flush_i), | |
| .ptw_active_o (ptw_active), | |
| .walking_instr_o (walking_instr), | |
| .ptw_error_o (ptw_error), | |
| .ptw_access_exception_o(ptw_access_exception), | |
| .enable_translation_i (enable_translation_i), | |
| .en_ld_st_translation_i(en_ld_st_translation_i), | |
| .lsu_is_store_i(lsu_is_store_i), | |
| output logic itlb_miss_o, | |
| output logic dtlb_miss_o, |
Comment on lines
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| .req_port_i (req_port_i), | ||
| .req_port_o (req_port_o), | ||
|
|
||
| .asid_i(asid_i), | ||
|
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| .update_vaddr_o(update_vaddr), | ||
|
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| // to Shared TLB, update logic | ||
| .shared_tlb_update_o(update_shared_tlb), | ||
|
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|
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| // from shared TLB | ||
| // did we miss? | ||
| .shared_tlb_access_i(shared_tlb_access), | ||
| .shared_tlb_hit_i (shared_tlb_hit), | ||
| .shared_tlb_vaddr_i (shared_tlb_vaddr), | ||
|
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| .itlb_req_i(itlb_req), | ||
|
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| .hlvx_inst_i(hlvx_inst_i), | ||
| // from CSR file | ||
| .satp_ppn_i (satp_ppn_i), | ||
| .mxr_i (mxr_i), | ||
|
|
||
| // Performance counters | ||
| .shared_tlb_miss_o(shared_tlb_miss), //open for now | ||
|
|
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| .req_port_i (req_port_i), | |
| .req_port_o (req_port_o), | |
| .asid_i(asid_i), | |
| .update_vaddr_o(update_vaddr), | |
| // to Shared TLB, update logic | |
| .shared_tlb_update_o(update_shared_tlb), | |
| // from shared TLB | |
| // did we miss? | |
| .shared_tlb_access_i(shared_tlb_access), | |
| .shared_tlb_hit_i (shared_tlb_hit), | |
| .shared_tlb_vaddr_i (shared_tlb_vaddr), | |
| .itlb_req_i(itlb_req), | |
| .hlvx_inst_i(hlvx_inst_i), | |
| // from CSR file | |
| .satp_ppn_i (satp_ppn_i), | |
| .mxr_i (mxr_i), | |
| // Performance counters | |
| .shared_tlb_miss_o(shared_tlb_miss), //open for now | |
| input dcache_req_o_t req_port_i, | |
| output dcache_req_i_t req_port_o, |
Comment on lines
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| lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[0][PPNWMin:12]; | ||
| lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[0][PPNWMin:12]; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[0][PPNWMin:12]; | |
| lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[0][PPNWMin:12]; | |
| lsu_dtlb_ppn_o = (en_ld_st_translation_i[HYP_EXT] && HYP_EXT == 1)? dtlb_content[HYP_EXT].ppn :dtlb_content[0].ppn; | |
| lsu_paddr_o = { | |
| (en_ld_st_translation_i[HYP_EXT] && HYP_EXT == 1)? dtlb_pte_q[HYP_EXT].ppn : dtlb_pte_q[0].ppn, | |
| lsu_vaddr_q[0][11:0] | |
| }; | |
| // Mega page | |
| if (dtlb_is_page_q[0]) begin |
| lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[0][PPNWMin:12]; | ||
| lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[0][PPNWMin:12]; | ||
|
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||
| end else if (PT_LEVELS == 3 && dtlb_is_page_q[PT_LEVELS-2]) begin |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| end else if (PT_LEVELS == 3 && dtlb_is_page_q[PT_LEVELS-2]) begin | |
| lsu_dtlb_ppn_o[PPNWMin:12] = lsu_vaddr_n[0][PPNWMin:12]; | |
| lsu_paddr_o[PPNWMin:12] = lsu_vaddr_q[0][PPNWMin:12]; |
Comment on lines
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| lsu_paddr_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_q[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; | ||
| lsu_dtlb_ppn_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_n[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| lsu_paddr_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_q[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; | |
| lsu_dtlb_ppn_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_n[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; | |
| end else if (PT_LEVELS == 3 && dtlb_is_page_q[PT_LEVELS-2]) begin |
| lsu_paddr_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_q[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; | ||
| lsu_dtlb_ppn_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_n[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; | ||
|
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||
| end |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| end | |
| lsu_paddr_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_q[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; | |
| lsu_dtlb_ppn_o[PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS] = lsu_vaddr_n[0][PPNWMin-(VPN_LEN/PT_LEVELS):9+PT_LEVELS]; |
Comment on lines
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| // physical memory based exceptions are ACCESS_FAULTS (PMA/PMP) | ||
|
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||
| // this is a store | ||
| if (lsu_is_store_q) begin | ||
| // check if the page is write-able and we are not violating privileges | ||
| // also check if the dirty flag is set | ||
| if(HYP_EXT==1 && en_ld_st_translation_i[HYP_EXT] && (!dtlb_pte_q[HYP_EXT].w || daccess_err[HYP_EXT] || !dtlb_pte_q[HYP_EXT].d)) begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::STORE_GUEST_PAGE_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| lsu_vaddr_q[HYP_EXT][(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : riscv::GPLEN)-1:0], | ||
| {CVA6Cfg.XLEN{1'b0}}, | ||
| en_ld_st_translation_i[HYP_EXT*2], | ||
| 1'b1 | ||
| }); | ||
| end else if ((en_ld_st_translation_i[0] || HYP_EXT==0) && (!dtlb_pte_q[0].w || daccess_err[0] || !dtlb_pte_q[0].d)) begin | ||
| if (HYP_EXT == 1) begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::STORE_PAGE_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| {riscv::GPLEN{1'b0}}, | ||
| lsu_tinst_q, | ||
| en_ld_st_translation_i[HYP_EXT*2], | ||
| 1'b1 | ||
| }); | ||
| end else begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::STORE_PAGE_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| 1'b1 | ||
| }); | ||
| end | ||
| // Check if any PMPs are violated | ||
| end else if (!pmp_data_allow) begin | ||
| if (HYP_EXT == 1) begin | ||
| lsu_exception_o =exception_t'({ | ||
| riscv::ST_ACCESS_FAULT, | ||
| {CVA6Cfg.XLEN'(lsu_paddr_o)}, | ||
| {riscv::GPLEN{1'b0}}, | ||
| lsu_tinst_q, | ||
| en_ld_st_translation_i[HYP_EXT*2], | ||
| 1'b1 | ||
| }); | ||
| end else begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::ST_ACCESS_FAULT, | ||
| CVA6Cfg.XLEN'(lsu_paddr_o[CVA6Cfg.PLEN-1:(CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? (CVA6Cfg.PLEN - CVA6Cfg.VLEN) : 0]), | ||
| 1'b1 | ||
| }); | ||
| end | ||
| end | ||
|
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||
| // this is a load | ||
| end else begin | ||
| if (HYP_EXT == 1 && daccess_err[HYP_EXT]) begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::LOAD_GUEST_PAGE_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| lsu_vaddr_q[HYP_EXT][(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : riscv::GPLEN)-1:0], | ||
| {CVA6Cfg.XLEN{1'b0}}, | ||
| en_ld_st_translation_i[HYP_EXT*2], | ||
| 1'b1 | ||
| }); | ||
| // check for sufficient access privileges - throw a page fault if necessary | ||
| end else if (daccess_err[0]) begin | ||
| if (HYP_EXT == 1) begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::LOAD_PAGE_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| {riscv::GPLEN{1'b0}}, | ||
| lsu_tinst_q, | ||
| en_ld_st_translation_i[HYP_EXT*2], | ||
| 1'b1 | ||
| }); | ||
| end else begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::LOAD_PAGE_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| 1'b1 | ||
| }); | ||
| end | ||
| // Check if any PMPs are violated | ||
| end else if (!pmp_data_allow) begin | ||
| if (HYP_EXT == 1) begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::LD_ACCESS_FAULT, | ||
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | ||
| {riscv::GPLEN{1'b0}}, | ||
| lsu_tinst_q, | ||
| en_ld_st_translation_i[HYP_EXT*2], | ||
| 1'b1 | ||
| }); | ||
| end else begin | ||
| lsu_exception_o = exception_t'({ | ||
| riscv::LD_ACCESS_FAULT, | ||
| lsu_paddr_o[CVA6Cfg.PLEN-1:(CVA6Cfg.PLEN>CVA6Cfg.VLEN)?(CVA6Cfg.PLEN-CVA6Cfg.VLEN) : 0], | ||
| 1'b1 | ||
| }); | ||
| end | ||
| end |
There was a problem hiding this comment.
[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| // --------- | |
| // DTLB Hit | |
| // -------- | |
| if (dtlb_hit_q && lsu_req_q) begin | |
| lsu_valid_o = 1'b1; | |
| // exception priority: | |
| // PAGE_FAULTS have higher priority than ACCESS_FAULTS | |
| // virtual memory based exceptions are PAGE_FAULTS | |
| // physical memory based exceptions are ACCESS_FAULTS (PMA/PMP) | |
| // this is a store | |
| if (lsu_is_store_q) begin | |
| // check if the page is write-able and we are not violating privileges | |
| // also check if the dirty flag is set | |
| if(HYP_EXT==1 && en_ld_st_translation_i[HYP_EXT] && (!dtlb_pte_q[HYP_EXT].w || daccess_err[HYP_EXT] || !dtlb_pte_q[HYP_EXT].d)) begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::STORE_GUEST_PAGE_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| lsu_vaddr_q[HYP_EXT][(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : riscv::GPLEN)-1:0], | |
| {CVA6Cfg.XLEN{1'b0}}, | |
| en_ld_st_translation_i[HYP_EXT*2], | |
| 1'b1 | |
| }); | |
| end else if ((en_ld_st_translation_i[0] || HYP_EXT==0) && (!dtlb_pte_q[0].w || daccess_err[0] || !dtlb_pte_q[0].d)) begin | |
| if (HYP_EXT == 1) begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::STORE_PAGE_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| {riscv::GPLEN{1'b0}}, | |
| lsu_tinst_q, | |
| en_ld_st_translation_i[HYP_EXT*2], | |
| 1'b1 | |
| }); | |
| end else begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::STORE_PAGE_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| 1'b1 | |
| }); | |
| end | |
| // Check if any PMPs are violated | |
| end else if (!pmp_data_allow) begin | |
| if (HYP_EXT == 1) begin | |
| lsu_exception_o =exception_t'({ | |
| riscv::ST_ACCESS_FAULT, | |
| {CVA6Cfg.XLEN'(lsu_paddr_o)}, | |
| {riscv::GPLEN{1'b0}}, | |
| lsu_tinst_q, | |
| en_ld_st_translation_i[HYP_EXT*2], | |
| 1'b1 | |
| }); | |
| end else begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::ST_ACCESS_FAULT, | |
| CVA6Cfg.XLEN'(lsu_paddr_o[CVA6Cfg.PLEN-1:(CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? (CVA6Cfg.PLEN - CVA6Cfg.VLEN) : 0]), | |
| 1'b1 | |
| }); | |
| end | |
| end | |
| // this is a load | |
| end else begin | |
| if (HYP_EXT == 1 && daccess_err[HYP_EXT]) begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::LOAD_GUEST_PAGE_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| lsu_vaddr_q[HYP_EXT][(CVA6Cfg.XLEN==32?CVA6Cfg.VLEN : riscv::GPLEN)-1:0], | |
| {CVA6Cfg.XLEN{1'b0}}, | |
| en_ld_st_translation_i[HYP_EXT*2], | |
| 1'b1 | |
| }); | |
| // check for sufficient access privileges - throw a page fault if necessary | |
| end else if (daccess_err[0]) begin | |
| if (HYP_EXT == 1) begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::LOAD_PAGE_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| {riscv::GPLEN{1'b0}}, | |
| lsu_tinst_q, | |
| en_ld_st_translation_i[HYP_EXT*2], | |
| 1'b1 | |
| }); | |
| end else begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::LOAD_PAGE_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| 1'b1 | |
| }); | |
| end | |
| // Check if any PMPs are violated | |
| end else if (!pmp_data_allow) begin | |
| if (HYP_EXT == 1) begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::LD_ACCESS_FAULT, | |
| {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[0][CVA6Cfg.VLEN-1]}}, lsu_vaddr_q[0]}, | |
| {riscv::GPLEN{1'b0}}, | |
| lsu_tinst_q, | |
| en_ld_st_translation_i[HYP_EXT*2], | |
| 1'b1 | |
| }); | |
| end else begin | |
| lsu_exception_o = exception_t'({ | |
| riscv::LD_ACCESS_FAULT, | |
| lsu_paddr_o[CVA6Cfg.PLEN-1:(CVA6Cfg.PLEN>CVA6Cfg.VLEN)?(CVA6Cfg.PLEN-CVA6Cfg.VLEN) : 0], | |
| 1'b1 | |
| }); | |
| end | |
| end |
|
✔️ successful run, report available here. |
|
Superseeded bby #1958 |
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New attempt of MMU unification