transform rvfi types into macros

Flist.ariane

@@ -15,6 +15,7 @@
 // Author: Michael Schaffner <[email protected]>, ETH Zurich
 // Date: 15.08.2018
 // Description: File list for OpenPiton flow
++incdir+core/include/
 +incdir+vendor/pulp-platform/common_cells/include/
 +incdir+common/local/util/
 +incdir+corev_apu/register_interface/include/

Makefile

@@ -240,7 +240,8 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
           $(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \
           $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/ \
           $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \
-          $(CVA6_REPO_DIR)/verif/tb/core/
+          $(CVA6_REPO_DIR)/verif/tb/core/ \
+          $(CVA6_REPO_DIR)/core/include/
 
 # Compile and sim flags
 compile_flag     += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat +define+$(defines)

core/Flist.cva6

@@ -30,6 +30,7 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
 
++incdir+${CVA6_REPO_DIR}/core/include/
 +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
 +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
 +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/axi/include/

core/Flist.cva6_gate

@@ -8,6 +8,8 @@
 # Original Author: Jean-Roch COULON - Thales
 #
 
++incdir+${CVA6_REPO_DIR}/core/include/
+
 ${CVA6_REPO_DIR}/core/include/config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
 ${CVA6_REPO_DIR}/core/include/riscv_pkg.sv

core/csr_regfile.sv

@@ -20,6 +20,7 @@ module csr_regfile
     parameter type                   exception_t        = logic,
     parameter type                   irq_ctrl_t         = logic,
     parameter type                   scoreboard_entry_t = logic,
+    parameter type                   rvfi_probes_csr_t  = logic,
     parameter int                    AsidWidth          = 1,
     parameter int unsigned           MHPMCounterNum     = 6
 ) (

core/cva6.sv

@@ -12,6 +12,7 @@
 // Date: 19.03.2017
 // Description: CVA6 Top-level module
 
+`include "rvfi_types.svh"
 
 module cva6
   import ariane_pkg::*;
@@ -21,15 +22,23 @@ module cva6
         cva6_config_pkg::cva6_cfg
     ),
 
+    // RVFI PROBES
+    parameter type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg),
+    parameter type rvfi_probes_csr_t = `RVFI_PROBES_CSR_T(CVA6Cfg),
+    parameter type rvfi_probes_t = struct packed {
+      logic csr;
+      rvfi_probes_instr_t instr;
+    },
+
     // branchpredict scoreboard entry
     // this is the struct which we will inject into the pipeline to guide the various
     // units towards the correct branch decision and resolve
-    parameter type branchpredict_sbe_t = struct packed {
+    localparam type branchpredict_sbe_t = struct packed {
       cf_t                    cf;               // type of control flow prediction
       logic [riscv::VLEN-1:0] predict_address;  // target address at which to jump, or not
     },
 
-    parameter type exception_t = struct packed {
+    localparam type exception_t = struct packed {
       logic [riscv::XLEN-1:0] cause;  // cause of exception
       logic [riscv::XLEN-1:0] tval;  // additional information of causing exception (e.g.: instruction causing it),
       // address of LD/ST fault
@@ -38,25 +47,25 @@ module cva6
 
     // cache request ports
     // I$ address translation requests
-    parameter type icache_areq_t = struct packed {
+    localparam type icache_areq_t = struct packed {
       logic                   fetch_valid;      // address translation valid
       logic [riscv::PLEN-1:0] fetch_paddr;      // physical address in
       exception_t             fetch_exception;  // exception occurred during fetch
     },
-    parameter type icache_arsp_t = struct packed {
+    localparam type icache_arsp_t = struct packed {
       logic                   fetch_req;    // address translation request
       logic [riscv::VLEN-1:0] fetch_vaddr;  // virtual address out
     },
 
     // I$ data requests
-    parameter type icache_dreq_t = struct packed {
+    localparam type icache_dreq_t = struct packed {
       logic                   req;      // we request a new word
       logic                   kill_s1;  // kill the current request
       logic                   kill_s2;  // kill the last request
       logic                   spec;     // request is speculative
       logic [riscv::VLEN-1:0] vaddr;    // 1st cycle: 12 bit index is taken for lookup
     },
-    parameter type icache_drsp_t = struct packed {
+    localparam type icache_drsp_t = struct packed {
       logic                                    ready;  // icache is ready
       logic                                    valid;  // signals a valid read
       logic [ariane_pkg::FETCH_WIDTH-1:0]      data;   // 2+ cycle out: tag
@@ -67,15 +76,15 @@ module cva6
 
     // IF/ID Stage
     // store the decompressed instruction
-    parameter type fetch_entry_t = struct packed {
+    localparam type fetch_entry_t = struct packed {
       logic [riscv::VLEN-1:0] address;  // the address of the instructions from below
       logic [31:0] instruction;  // instruction word
       branchpredict_sbe_t     branch_predict; // this field contains branch prediction information regarding the forward branch path
       exception_t             ex;             // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions
     },
 
     // ID/EX/WB Stage
-    parameter type scoreboard_entry_t = struct packed {
+    localparam type scoreboard_entry_t = struct packed {
       logic [riscv::VLEN-1:0] pc;  // PC of instruction
       logic [TRANS_ID_BITS-1:0] trans_id;      // this can potentially be simplified, we could index the scoreboard entry
                                                // with the transaction id in any case make the width more generic
@@ -103,7 +112,7 @@ module cva6
     // this is the struct we get back from ex stage and we will use it to update
     // all the necessary data structures
     // bp_resolve_t
-    parameter type bp_resolve_t = struct packed {
+    localparam type bp_resolve_t = struct packed {
       logic                   valid;           // prediction with all its values is valid
       logic [riscv::VLEN-1:0] pc;              // PC of predict or mis-predict
       logic [riscv::VLEN-1:0] target_address;  // target address at which to jump, or not
@@ -114,15 +123,15 @@ module cva6
 
     // All information needed to determine whether we need to associate an interrupt
     // with the corresponding instruction or not.
-    parameter type irq_ctrl_t = struct packed {
+    localparam type irq_ctrl_t = struct packed {
       logic [riscv::XLEN-1:0] mie;
       logic [riscv::XLEN-1:0] mip;
       logic [riscv::XLEN-1:0] mideleg;
       logic                   sie;
       logic                   global_enable;
     },
 
-    parameter type lsu_ctrl_t = struct packed {
+    localparam type lsu_ctrl_t = struct packed {
       logic                                 valid;
       logic [riscv::VLEN-1:0]               vaddr;
       logic                                 overflow;
@@ -133,7 +142,7 @@ module cva6
       logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
     },
 
-    parameter type fu_data_t = struct packed {
+    localparam type fu_data_t = struct packed {
       fu_t                                  fu;
       fu_op                                 operation;
       logic [riscv::XLEN-1:0]               operand_a;
@@ -142,13 +151,13 @@ module cva6
       logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
     },
 
-    parameter type icache_req_t = struct packed {
+    localparam type icache_req_t = struct packed {
       logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way;  // way to replace
       logic [riscv::PLEN-1:0] paddr;  // physical address
       logic nc;  // noncacheable
       logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
     },
-    parameter type icache_rtrn_t = struct packed {
+    localparam type icache_rtrn_t = struct packed {
       wt_cache_pkg::icache_in_t rtype;  // see definitions above
       logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data;  // full cache line width
       logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user;  // user bits
@@ -162,7 +171,7 @@ module cva6
     },
 
     // D$ data requests
-    parameter type dcache_req_i_t = struct packed {
+    localparam type dcache_req_i_t = struct packed {
       logic [DCACHE_INDEX_WIDTH-1:0] address_index;
       logic [DCACHE_TAG_WIDTH-1:0]   address_tag;
       logic [riscv::XLEN-1:0]        data_wdata;
@@ -176,19 +185,14 @@ module cva6
       logic                          tag_valid;
     },
 
-    parameter type dcache_req_o_t = struct packed {
+    localparam type dcache_req_o_t = struct packed {
       logic                         data_gnt;
       logic                         data_rvalid;
       logic [DCACHE_TID_WIDTH-1:0]  data_rid;
       logic [riscv::XLEN-1:0]       data_rdata;
       logic [DCACHE_USER_WIDTH-1:0] data_ruser;
     },
 
-    parameter type rvfi_probes_t = struct packed {
-      logic csr;  //disabled 
-      rvfi_probes_instr_t instr;
-    },
-
     // AXI types
     parameter type axi_ar_chan_t = struct packed {
       logic [CVA6Cfg.AxiIdWidth-1:0]   id;
@@ -911,6 +915,7 @@ module cva6
       .exception_t       (exception_t),
       .irq_ctrl_t        (irq_ctrl_t),
       .scoreboard_entry_t(scoreboard_entry_t),
+      .rvfi_probes_csr_t (rvfi_probes_csr_t),
       .AsidWidth         (ASID_WIDTH),
       .MHPMCounterNum    (MHPMCounterNum)
   ) csr_regfile_i (
@@ -1510,11 +1515,13 @@ module cva6
   //RVFI INSTR
 
   cva6_rvfi_probes #(
-      .CVA6Cfg           (CVA6Cfg),
-      .exception_t       (exception_t),
-      .scoreboard_entry_t(scoreboard_entry_t),
-      .lsu_ctrl_t        (lsu_ctrl_t),
-      .rvfi_probes_t     (rvfi_probes_t)
+      .CVA6Cfg            (CVA6Cfg),
+      .exception_t        (exception_t),
+      .scoreboard_entry_t (scoreboard_entry_t),
+      .lsu_ctrl_t         (lsu_ctrl_t),
+      .rvfi_probes_instr_t(rvfi_probes_instr_t),
+      .rvfi_probes_csr_t  (rvfi_probes_csr_t),
+      .rvfi_probes_t      (rvfi_probes_t)
   ) i_cva6_rvfi_probes (
 
       .flush_i            (flush_ctrl_if),

core/cva6_rvfi.sv

@@ -15,6 +15,8 @@ module cva6_rvfi
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
     parameter type rvfi_instr_t = logic,
     parameter type rvfi_csr_t = logic,
+    parameter type rvfi_probes_instr_t = logic,
+    parameter type rvfi_probes_csr_t = logic,
     parameter type rvfi_probes_t = logic
 
 ) (

core/cva6_rvfi_probes.sv

@@ -16,6 +16,8 @@ module cva6_rvfi_probes
     parameter type exception_t = logic,
     parameter type scoreboard_entry_t = logic,
     parameter type lsu_ctrl_t = logic,
+    parameter type rvfi_probes_instr_t = logic,
+    parameter type rvfi_probes_csr_t = logic,
     parameter type rvfi_probes_t = logic
 
 ) (

core/include/ariane_pkg.sv

@@ -646,142 +646,6 @@ package ariane_pkg;
     logic [63:0] result;  // sign-extended, result
   } amo_resp_t;
 
-  // RVFI instr 
-  typedef struct packed {
-    logic [TRANS_ID_BITS-1:0] issue_pointer;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_pointer;
-    logic flush_unissued_instr;
-    logic decoded_instr_valid;
-    logic decoded_instr_ack;
-    logic flush;
-    logic issue_instr_ack;
-    logic fetch_entry_valid;
-    logic [31:0] instruction;
-    logic is_compressed;
-    riscv::xlen_t rs1_forwarding;
-    riscv::xlen_t rs2_forwarding;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_pc;
-    fu_op [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_instr_op;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs1;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rs2;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][REG_ADDR_SIZE-1:0] commit_instr_rd;
-    riscv::xlen_t [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_instr_result;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::VLEN-1:0] commit_instr_valid;
-    riscv::xlen_t ex_commit_cause;
-    logic ex_commit_valid;
-    riscv::priv_lvl_t priv_lvl;
-    logic [riscv::VLEN-1:0] lsu_ctrl_vaddr;
-    fu_t lsu_ctrl_fu;
-    logic [(riscv::XLEN/8)-1:0] lsu_ctrl_be;
-    logic [TRANS_ID_BITS-1:0] lsu_ctrl_trans_id;
-    logic [((cva6_config_pkg::CVA6ConfigCvxifEn || cva6_config_pkg::CVA6ConfigVExtEn) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0] commit_ack;
-    logic [riscv::PLEN-1:0] mem_paddr;
-    logic debug_mode;
-    logic [cva6_config_pkg::CVA6ConfigNrCommitPorts-1:0][riscv::XLEN-1:0] wdata;
-  } rvfi_probes_instr_t;
-
-  // RVFI CSR element
-  typedef struct packed {
-    riscv::xlen_t rdata;
-    riscv::xlen_t rmask;
-    riscv::xlen_t wdata;
-    riscv::xlen_t wmask;
-  } rvfi_csr_elmt_t;
-
-  // RVFI CSR structure
-  typedef struct packed {
-    riscv::fcsr_t fcsr_q;
-    riscv::dcsr_t dcsr_q;
-    riscv::xlen_t dpc_q;
-    riscv::xlen_t dscratch0_q;
-    riscv::xlen_t dscratch1_q;
-    riscv::xlen_t mie_q;
-    riscv::xlen_t mip_q;
-    riscv::xlen_t stvec_q;
-    riscv::xlen_t scounteren_q;
-    riscv::xlen_t sscratch_q;
-    riscv::xlen_t sepc_q;
-    riscv::xlen_t scause_q;
-    riscv::xlen_t stval_q;
-    riscv::xlen_t satp_q;
-    riscv::xlen_t mstatus_extended;
-    riscv::xlen_t medeleg_q;
-    riscv::xlen_t mideleg_q;
-    riscv::xlen_t mtvec_q;
-    riscv::xlen_t mcounteren_q;
-    riscv::xlen_t mscratch_q;
-    riscv::xlen_t mepc_q;
-    riscv::xlen_t mcause_q;
-    riscv::xlen_t mtval_q;
-    logic fiom_q;
-    logic [MHPMCounterNum+3-1:0] mcountinhibit_q;
-    logic [63:0] cycle_q;
-    logic [63:0] instret_q;
-    riscv::xlen_t dcache_q;
-    riscv::xlen_t icache_q;
-    riscv::xlen_t acc_cons_q;
-    riscv::pmpcfg_t [15:0] pmpcfg_q;
-    logic [15:0][riscv::PLEN-3:0] pmpaddr_q;
-  } rvfi_probes_csr_t;
-
-  // RVFI CSR structure
-  typedef struct packed {
-    rvfi_csr_elmt_t fflags;
-    rvfi_csr_elmt_t frm;
-    rvfi_csr_elmt_t fcsr;
-    rvfi_csr_elmt_t ftran;
-    rvfi_csr_elmt_t dcsr;
-    rvfi_csr_elmt_t dpc;
-    rvfi_csr_elmt_t dscratch0;
-    rvfi_csr_elmt_t dscratch1;
-    rvfi_csr_elmt_t sstatus;
-    rvfi_csr_elmt_t sie;
-    rvfi_csr_elmt_t sip;
-    rvfi_csr_elmt_t stvec;
-    rvfi_csr_elmt_t scounteren;
-    rvfi_csr_elmt_t sscratch;
-    rvfi_csr_elmt_t sepc;
-    rvfi_csr_elmt_t scause;
-    rvfi_csr_elmt_t stval;
-    rvfi_csr_elmt_t satp;
-    rvfi_csr_elmt_t mstatus;
-    rvfi_csr_elmt_t mstatush;
-    rvfi_csr_elmt_t misa;
-    rvfi_csr_elmt_t medeleg;
-    rvfi_csr_elmt_t mideleg;
-    rvfi_csr_elmt_t mie;
-    rvfi_csr_elmt_t mtvec;
-    rvfi_csr_elmt_t mcounteren;
-    rvfi_csr_elmt_t mscratch;
-    rvfi_csr_elmt_t mepc;
-    rvfi_csr_elmt_t mcause;
-    rvfi_csr_elmt_t mtval;
-    rvfi_csr_elmt_t mip;
-    rvfi_csr_elmt_t menvcfg;
-    rvfi_csr_elmt_t menvcfgh;
-    rvfi_csr_elmt_t mvendorid;
-    rvfi_csr_elmt_t marchid;
-    rvfi_csr_elmt_t mhartid;
-    rvfi_csr_elmt_t mcountinhibit;
-    rvfi_csr_elmt_t mcycle;
-    rvfi_csr_elmt_t mcycleh;
-    rvfi_csr_elmt_t minstret;
-    rvfi_csr_elmt_t minstreth;
-    rvfi_csr_elmt_t cycle;
-    rvfi_csr_elmt_t cycleh;
-    rvfi_csr_elmt_t instret;
-    rvfi_csr_elmt_t instreth;
-    rvfi_csr_elmt_t dcache;
-    rvfi_csr_elmt_t icache;
-    rvfi_csr_elmt_t acc_cons;
-    rvfi_csr_elmt_t pmpcfg0;
-    rvfi_csr_elmt_t pmpcfg1;
-    rvfi_csr_elmt_t pmpcfg2;
-    rvfi_csr_elmt_t pmpcfg3;
-    rvfi_csr_elmt_t [15:0] pmpaddr;
-  } rvfi_csr_t;
-
   localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace;
 
   // ----------------------