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Zcmp ext #1765

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Zcmp ext #1765

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2deaf00
Add Zcmp support
gullahmed1 Jan 12, 2024
237d62f
Add Zcmp support v2
gullahmed1 Jan 16, 2024
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1 change: 1 addition & 0 deletions core/Flist.cva6
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Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,7 @@ ${CVA6_REPO_DIR}/core/alu.sv
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/zcmp_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
Expand Down
9 changes: 7 additions & 2 deletions core/compressed_decoder.sv
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Expand Up @@ -24,6 +24,7 @@
) (
input logic [31:0] instr_i,
output logic [31:0] instr_o,
output logic is_push_pop_instr_o,
output logic illegal_instr_o,
output logic is_compressed_o
);
Expand All @@ -32,10 +33,11 @@
// Compressed Decoder
// -------------------
always_comb begin
illegal_instr_o = 1'b0;

Check warning on line 36 in core/compressed_decoder.sv

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
core/compressed_decoder.sv:36:-    illegal_instr_o = 1'b0;
core/compressed_decoder.sv:37:-    instr_o         = '0;
core/compressed_decoder.sv:38:-    is_compressed_o = 1'b1;
core/compressed_decoder.sv:39:-    instr_o         = instr_i;
core/compressed_decoder.sv:36:+    illegal_instr_o     = 1'b0;
core/compressed_decoder.sv:37:+    instr_o             = '0;
core/compressed_decoder.sv:38:+    is_compressed_o     = 1'b1;
core/compressed_decoder.sv:39:+    instr_o             = instr_i;
instr_o = '0;
is_compressed_o = 1'b1;
instr_o = instr_i;
is_push_pop_instr_o = 0;

// I: | imm[11:0] | rs1 | funct3 | rd | opcode |
// S: | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
Expand Down Expand Up @@ -848,7 +850,10 @@
end

riscv::OpcodeC2Fsdsp: begin
if (CVA6Cfg.FpPresent) begin
if (instr_i[12:10] == 3'b110 || instr_i[12:10] == 3'b111 || instr_i[12:10] == 3'b011) begin //is a push/pop instruction
is_push_pop_instr_o = 1;
instr_o = instr_i;
Comment on lines +854 to +855
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
is_push_pop_instr_o = 1;
instr_o = instr_i;
is_push_pop_instr_o = 1;
instr_o = instr_i;

end else if (CVA6Cfg.FpPresent) begin
// c.fsdsp -> fsd rs2, imm(x2)
instr_o = {
3'b0,
Expand All @@ -861,7 +866,7 @@
3'b000,
riscv::OpcodeStoreFp
};
end else begin
end else begin
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
end else begin
end else begin

illegal_instr_o = 1'b1;
end
end
Expand Down
31 changes: 26 additions & 5 deletions core/id_stage.sv
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Expand Up @@ -54,8 +54,13 @@ module id_stage #(
ariane_pkg::scoreboard_entry_t decoded_instruction;

logic is_illegal;
logic is_illegal_cmp;
logic [31:0] instruction;
logic [31:0] compressed_instr;
logic is_compressed;
logic is_compressed_cmp;
logic is_push_pop;
logic stall_instr_fetch;

if (CVA6Cfg.RVC) begin
// ---------------------------------------------------------
Expand All @@ -65,10 +70,26 @@ module id_stage #(
.CVA6Cfg(CVA6Cfg)
) compressed_decoder_i (
.instr_i (fetch_entry_i.instruction),
.instr_o (instruction),
.instr_o (compressed_instr),
.illegal_instr_o(is_illegal),
.is_compressed_o(is_compressed)
.is_compressed_o(is_compressed),
Comment on lines 72 to +75
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
.instr_i (fetch_entry_i.instruction),
.instr_o (instruction),
.instr_o (compressed_instr),
.illegal_instr_o(is_illegal),
.is_compressed_o(is_compressed)
.is_compressed_o(is_compressed),
.instr_i (fetch_entry_i.instruction),
.instr_o (compressed_instr),
.illegal_instr_o (is_illegal),
.is_compressed_o (is_compressed),

.is_push_pop_instr_o(is_push_pop)
);
//sequencial decoder
zcmp_decoder #(
Comment on lines +78 to +79
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
//sequencial decoder
zcmp_decoder #(
//sequencial decoder
zcmp_decoder #(

.CVA6Cfg(CVA6Cfg)
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_push_pop_instr_i (is_push_pop),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall (stall_instr_fetch)
);
Comment on lines +81 to +92
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_push_pop_instr_i (is_push_pop),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall (stall_instr_fetch)
);
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_push_pop_instr_i(is_push_pop),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall (stall_instr_fetch)
);

end else begin
assign instruction = fetch_entry_i.instruction;
assign is_illegal = '0;
Expand All @@ -84,8 +105,8 @@ module id_stage #(
.irq_ctrl_i,
.irq_i,
.pc_i (fetch_entry_i.address),
.is_compressed_i (is_compressed),
.is_illegal_i (is_illegal),
.is_compressed_i (is_compressed_cmp),
.is_illegal_i (is_illegal_cmp),
.instruction_i (instruction),
.compressed_instr_i (fetch_entry_i.instruction[15:0]),
.branch_predict_i (fetch_entry_i.branch_predict),
Expand Down Expand Up @@ -119,7 +140,7 @@ module id_stage #(
// if we have a space in the register and the fetch is valid, go get it
// or the issue stage is currently acknowledging an instruction, which means that we will have space
// for a new instruction
if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i) begin
if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i && !stall_instr_fetch) begin
fetch_entry_ready_o = 1'b1;
issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
end
Expand Down
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