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Zcmp ext #1765

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Zcmp ext #1765

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gullahmed1
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@gullahmed1 gullahmed1 closed this Jan 16, 2024
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github-actions bot reviewed Jan 16, 2024
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Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/zcmp_decoder.sv|239|
core/zcmp_decoder.sv|241|
core/zcmp_decoder.sv|245|
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core/compressed_decoder.sv
Comment on lines +854 to +855
is_push_pop_instr_o = 1;
instr_o = instr_i;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
is_push_pop_instr_o = 1;
instr_o = instr_i;
is_push_pop_instr_o = 1;
instr_o = instr_i;

core/compressed_decoder.sv
@@ -861,7 +866,7 @@ module compressed_decoder #(
3'b000,
riscv::OpcodeStoreFp
};
end else begin
end else begin
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
end else begin
end else begin

core/id_stage.sv
Comment on lines 72 to +75
.instr_i (fetch_entry_i.instruction),
.instr_o (instruction),
.instr_o (compressed_instr),
.illegal_instr_o(is_illegal),
.is_compressed_o(is_compressed)
.is_compressed_o(is_compressed),
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
.instr_i (fetch_entry_i.instruction),
.instr_o (instruction),
.instr_o (compressed_instr),
.illegal_instr_o(is_illegal),
.is_compressed_o(is_compressed)
.is_compressed_o(is_compressed),
.instr_i (fetch_entry_i.instruction),
.instr_o (compressed_instr),
.illegal_instr_o (is_illegal),
.is_compressed_o (is_compressed),

core/id_stage.sv
Comment on lines +78 to +79
//sequencial decoder
zcmp_decoder #(
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
//sequencial decoder
zcmp_decoder #(
//sequencial decoder
zcmp_decoder #(

core/id_stage.sv
Comment on lines +81 to +92
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_push_pop_instr_i (is_push_pop),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall (stall_instr_fetch)
);
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_push_pop_instr_i (is_push_pop),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall (stall_instr_fetch)
);
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_push_pop_instr_i(is_push_pop),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall (stall_instr_fetch)
);

core/zcmp_decoder.sv
xreg2 = {instr_i[4:3] > 0, instr_i[4:3] == 0, instr_i[4:2]};
end else begin
illegal_instr_o = 1'b1;
end
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
end
end

core/zcmp_decoder.sv
xreg1 = '0;
xreg2 = '0;
end

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[verible-verilog-format] reported by reviewdog 🐶

Suggested change

core/zcmp_decoder.sv
Comment on lines +119 to +130
4'b0100: reg_numbers = 4'b0001; // 4
4'b0101: reg_numbers = 4'b0010; // 5
4'b0110: reg_numbers = 4'b0011; // 6
4'b0111: reg_numbers = 4'b0100; // 7
4'b1000: reg_numbers = 4'b0101; // 8
4'b1001: reg_numbers = 4'b0110; // 9
4'b1010: reg_numbers = 4'b0111; // 10
4'b1011: reg_numbers = 4'b1000; // 11
4'b1100: reg_numbers = 4'b1001; // 12
4'b1101: reg_numbers = 4'b1010; // 13
4'b1110: reg_numbers = 4'b1011; // 14
4'b1111: reg_numbers = 4'b1100; // 15
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
4'b0100: reg_numbers = 4'b0001; // 4
4'b0101: reg_numbers = 4'b0010; // 5
4'b0110: reg_numbers = 4'b0011; // 6
4'b0111: reg_numbers = 4'b0100; // 7
4'b1000: reg_numbers = 4'b0101; // 8
4'b1001: reg_numbers = 4'b0110; // 9
4'b1010: reg_numbers = 4'b0111; // 10
4'b1011: reg_numbers = 4'b1000; // 11
4'b1100: reg_numbers = 4'b1001; // 12
4'b1101: reg_numbers = 4'b1010; // 13
4'b1110: reg_numbers = 4'b1011; // 14
4'b1111: reg_numbers = 4'b1100; // 15
4'b0100: reg_numbers = 4'b0001; // 4
4'b0101: reg_numbers = 4'b0010; // 5
4'b0110: reg_numbers = 4'b0011; // 6
4'b0111: reg_numbers = 4'b0100; // 7
4'b1000: reg_numbers = 4'b0101; // 8
4'b1001: reg_numbers = 4'b0110; // 9
4'b1010: reg_numbers = 4'b0111; // 10
4'b1011: reg_numbers = 4'b1000; // 11
4'b1100: reg_numbers = 4'b1001; // 12
4'b1101: reg_numbers = 4'b1010; // 13
4'b1110: reg_numbers = 4'b1011; // 14
4'b1111: reg_numbers = 4'b1100; // 15

core/zcmp_decoder.sv
default: illegal_instr_o = 1'b1;
endcase

if (riscv::XLEN==32) begin
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
if (riscv::XLEN==32) begin
if (riscv::XLEN == 32) begin

core/zcmp_decoder.sv
end

//Take 2's compliment in case of PUSH instruction
if(zcmp_instr_type == PUSH) begin
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
if(zcmp_instr_type == PUSH) begin
if (zcmp_instr_type == PUSH) begin

@JeanRochCoulon
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@gullahmed1 Thanks you for the contribution. To avoid RTL reformating, you need to run Verible on your code before submitting the PR.

@JeanRochCoulon
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Some Verible recommandations in contributing.md file

Gchauvon pushed a commit to Gchauvon/cva6 that referenced this pull request Jan 24, 2024
@JeanRochCoulon
Merge pull request openhwgroup#1765 from zchamski/cvvdev/dev/verilato…
a2b8835 
…r-v5

Switch Verilator testing to use v5.008 instead of v4.110
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@JeanRochCoulon JeanRochCoulon Awaiting requested review from JeanRochCoulon JeanRochCoulon is a code owner

@zarubaf zarubaf Awaiting requested review from zarubaf zarubaf is a code owner

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@gullahmed1 @JeanRochCoulon