Mmu unify - task1

Bender.yml

@@ -48,29 +48,32 @@ sources:
           - core/include/cv32a6_imac_sv0_config_pkg.sv
           - core/include/riscv_pkg.sv
           - core/include/ariane_pkg.sv
-          - core/mmu_sv32/cva6_tlb_sv32.sv
-          - core/mmu_sv32/cva6_mmu_sv32.sv
+          - core/mmu_unify/cva6_tlb.sv
+          - core/mmu_unify/cva6_mmu.sv
           - core/mmu_sv32/cva6_ptw_sv32.sv
+          - core/mmu_unify/cva6_ptw.sv
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       - target: cv32a6_imac_sv32
         files:
           - core/include/cv32a6_imac_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
           - core/include/ariane_pkg.sv
-          - core/mmu_sv32/cva6_tlb_sv32.sv
-          - core/mmu_sv32/cva6_mmu_sv32.sv
+          - core/mmu_unify/cva6_tlb.sv
+          - core/mmu_unify/cva6_mmu.sv
           - core/mmu_sv32/cva6_ptw_sv32.sv
+          - core/mmu_unify/cva6_ptw.sv
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       - target: cv32a6_imafc_sv32
         files:
           - core/include/cv32a6_imafc_sv32_config_pkg.sv
           - core/include/riscv_pkg.sv
           - core/include/ariane_pkg.sv
-          - core/mmu_sv32/cva6_tlb_sv32.sv
-          - core/mmu_sv32/cva6_mmu_sv32.sv
+          - core/mmu_unify/cva6_tlb.sv
+          - core/mmu_unify/cva6_mmu.sv
           - core/mmu_sv32/cva6_ptw_sv32.sv
+          - core/mmu_unify/cva6_ptw.sv
           - core/cva6_accel_first_pass_decoder_stub.sv
 
       # included via target core/include/${TARGET_CFG}_config_pkg.sv

ariane.core

@@ -35,18 +35,21 @@ filesets:
       - src/miss_handler.sv
       - src/mmu_sv39/mmu.sv
       - src/mmu_sv32/cva6_mmu_sv32.sv
+      - src/mmu_unify/cva6_mmu.sv
       - src/mult.sv
       - src/nbdcache.sv
       - src/pcgen_stage.sv
       - src/perf_counters.sv
       - src/mmu_sv39/ptw.sv
       - src/mmu_sv32/cva6_ptw_sv32.sv
+      - src/mmu_unify/cva6_ptw.sv
       - src/regfile_ff.sv
       - src/scoreboard.sv
       - src/store_buffer.sv
       - src/store_unit.sv
       - src/mmu_sv39/tlb.sv
       - src/mmu_sv32/cva6_tlb_sv32.sv
+      - src/mmu_unify/cva6_tlb.sv
     file_type : systemVerilogSource
     depend :
       - pulp-platform.org::axi_mem_if

core/Flist.cva6

@@ -187,4 +187,10 @@ ${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
 ${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
 ${CVA6_REPO_DIR}/core/mmu_sv32/cva6_shared_tlb_sv32.sv
 
+// MMU Unify
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_mmu.sv
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_tlb.sv
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_shared_tlb.sv
+${CVA6_REPO_DIR}/core/mmu_unify/cva6_ptw.sv
+
 // end of manifest

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -55,8 +55,8 @@ package cva6_config_pkg;
   localparam CVA6ConfigNrStorePipeRegs = 0;
   localparam CVA6ConfigNrLoadBufEntries = 2;
 
-  localparam CVA6ConfigInstrTlbEntries = 16;
-  localparam CVA6ConfigDataTlbEntries = 16;
+  localparam CVA6ConfigInstrTlbEntries = 2;
+  localparam CVA6ConfigDataTlbEntries = 2;
 
   localparam CVA6ConfigRASDepth = 2;
   localparam CVA6ConfigBTBEntries = 32;

core/load_store_unit.sv

@@ -140,41 +140,20 @@ module load_store_unit
   // -------------------
   // MMU e.g.: TLBs/PTW
   // -------------------
-  if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39
-    mmu #(
-        .CVA6Cfg          (CVA6Cfg),
-        .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
-        .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
-        .ASID_WIDTH       (ASID_WIDTH)
-    ) i_cva6_mmu (
-        // misaligned bypass
-        .misaligned_ex_i(misaligned_exception),
-        .lsu_is_store_i (st_translation_req),
-        .lsu_req_i      (translation_req),
-        .lsu_vaddr_i    (mmu_vaddr),
-        .lsu_valid_o    (translation_valid),
-        .lsu_paddr_o    (mmu_paddr),
-        .lsu_exception_o(mmu_exception),
-        .lsu_dtlb_hit_o (dtlb_hit),               // send in the same cycle as the request
-        .lsu_dtlb_ppn_o (dtlb_ppn),               // send in the same cycle as the request
-        // connecting PTW to D$ IF
-        .req_port_i     (dcache_req_ports_i[0]),
-        .req_port_o     (dcache_req_ports_o[0]),
-        // icache address translation requests
-        .icache_areq_i  (icache_areq_i),
-        .asid_to_be_flushed_i,
-        .vaddr_to_be_flushed_i,
-        .icache_areq_o  (icache_areq_o),
-        .pmpcfg_i,
-        .pmpaddr_i,
-        .*
-    );
-  end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32
-    cva6_mmu_sv32 #(
+  if (MMU_PRESENT) begin : gen_mmu
+
+    localparam ASID_LEN = (riscv::XLEN == 64) ? 16 : 9;
+    localparam VPN_LEN = (riscv::XLEN == 64) ? 27 : 20;
+    localparam PT_LEVELS = (riscv::XLEN == 64) ? 3 : 2;
+
+    cva6_mmu #(
         .CVA6Cfg          (CVA6Cfg),
         .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES),
         .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES),
-        .ASID_WIDTH       (ASID_WIDTH)
+        .ASID_WIDTH       (ASID_WIDTH),
+        .ASID_LEN         (ASID_LEN),
+        .VPN_LEN          (VPN_LEN),
+        .PT_LEVELS        (PT_LEVELS)
     ) i_cva6_mmu (
         // misaligned bypass
         .misaligned_ex_i(misaligned_exception),

core/mmu_unify/README.md

@@ -0,0 +1 @@
+Unification of MMUs: sv32, sv39 and sv39x4