Mmu unify - task1

[AngelaGonzalezMarino]

Merge of sv32 and sv39 MMUs. Parametrization strategy followed for new parameters.

[github-actions]

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/mmu_unify/cva6_mmu.sv|623|
core/mmu_unify/cva6_ptw.sv|37|
core/mmu_unify/cva6_ptw.sv|102|
core/mmu_unify/cva6_ptw.sv|113|
core/mmu_unify/cva6_ptw.sv|139|
core/mmu_unify/cva6_ptw.sv|143|
core/mmu_unify/cva6_ptw.sv|146|
core/mmu_unify/cva6_ptw.sv|151|
core/mmu_unify/cva6_ptw.sv|156|
core/mmu_unify/cva6_ptw.sv|189|
core/mmu_unify/cva6_ptw.sv|247|
core/mmu_unify/cva6_shared_tlb.sv|167|
core/mmu_unify/cva6_tlb.sv|204|

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic itlb_lu_access;
	logic itlb_lu_access;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic [PT_LEVELS-2:0] itlb_is_page;
	logic itlb_lu_hit;
	logic [ PT_LEVELS-2:0] itlb_is_page;
	logic itlb_lu_hit;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic dtlb_lu_access;
	logic dtlb_lu_access;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic [PT_LEVELS-2:0] dtlb_is_page;
	logic dtlb_lu_hit;
	logic [ PT_LEVELS-2:0] dtlb_is_page;
	logic dtlb_lu_hit;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic shared_tlb_access;
	logic [riscv::VLEN-1:0] shared_tlb_vaddr;
	logic shared_tlb_hit;
	logic shared_tlb_access;
	logic [riscv::VLEN-1:0] shared_tlb_vaddr;
	logic shared_tlb_hit;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	endmodule
	endmodule

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	assign req_port_o.data_be = riscv::XLEN ==32?
	be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size):
	be_gen(req_port_o.address_index[2:0], req_port_o.data_size);
	assign req_port_o.data_be = riscv::XLEN == 32 ? be_gen_32(
	req_port_o.address_index[1:0], req_port_o.data_size
	) : be_gen(
	req_port_o.address_index[2:0], req_port_o.data_size
	);

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin
	// we got a hit so update the pointer as it was least recently used
	for (
	int unsigned i = 0; i < TLB_ENTRIES; i++
	) begin
	// we got a hit so update the pointer as it was least recently used

[github-actions]

✔️ successful run, report available here.