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Code_coverage: condition RTL with the IS_XLEN64 parameter #1666

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merged 6 commits into from
Dec 4, 2023
Merged

Code_coverage: condition RTL with the IS_XLEN64 parameter #1666

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8af393e
Code_coverage: condition RTL with the IS_XLEN64 parameter
AEzzejjari Dec 1, 2023
e039f6a
Update decoder.sv
AEzzejjari Dec 4, 2023
542af3e
Update load_store_unit.sv
AEzzejjari Dec 4, 2023
95a993a
Merge branch 'master' into Xlen64_Delete
AEzzejjari Dec 4, 2023
4be0890
Update core/cache_subsystem/wt_axi_adapter.sv
AEzzejjari Dec 4, 2023
0166ad1
Update core/alu.sv
AEzzejjari Dec 4, 2023
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7 changes: 2 additions & 5 deletions core/alu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -284,9 +284,6 @@
endcase
end
unique case (fu_data_i.operation)
// Left Shift 32 bit unsigned
SLLIUW:
result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0];
// Integer minimum/maximum
MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a;
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a;
MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a;

MAXU: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a;
Expand Down Expand Up @@ -319,12 +316,12 @@
ROR, RORI:
result_o = (riscv::IS_XLEN64) ? ((fu_data_i.operand_a >> fu_data_i.operand_b[5:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[5:0]))) : ((fu_data_i.operand_a >> fu_data_i.operand_b[4:0]) | (fu_data_i.operand_a << (riscv::XLEN-fu_data_i.operand_b[4:0])));

ORCB:

Check warning on line 319 in core/alu.sv

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[verible-verilog-format] reported by reviewdog 🐶


Raw Output:
core/alu.sv:319:-        ORCB:
core/alu.sv:320:-        result_o = orcbw_result;
core/alu.sv:321:-        REV8:
core/alu.sv:322:-        result_o = rev8w_result;
core/alu.sv:341:+        ORCB: result_o = orcbw_result;
core/alu.sv:342:+        REV8: result_o = rev8w_result;
result_o = orcbw_result;
REV8:
result_o = rev8w_result;

default: ; // default case to suppress unique warning
// Left Shift 32 bit unsigned
default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning
default:
if (fu_data_i.operation == SLLIUW && riscv::IS_XLEN64)
result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning

endcase
end
if (CVA6Cfg.ZiCondExtEn) begin
Expand Down
2 changes: 1 addition & 1 deletion core/cache_subsystem/wt_axi_adapter.sv
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Expand Up @@ -205,7 +205,7 @@ module wt_axi_adapter
2'b10:
axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = '1; // word
default:
axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword
if (riscv::IS_XLEN64) axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword
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[verible-verilog-format] reported by reviewdog 🐶

Suggested change
if (riscv::IS_XLEN64) axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword
if (riscv::IS_XLEN64)
axi_wr_be[0][dcache_data.paddr[$clog2(
CVA6Cfg.AxiDataWidth/8
)-1:0]+:8] = '1; // dword

endcase
end
//////////////////////////////////////
Expand Down
4 changes: 2 additions & 2 deletions core/load_store_unit.sv
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Expand Up @@ -107,7 +107,7 @@ module load_store_unit
assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a));
assign vaddr_i = vaddr_xlen[riscv::VLEN-1:0];
// we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal
assign overflow = !((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0);
assign overflow = (riscv::IS_XLEN64 && !((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0));

logic st_valid_i;
logic ld_valid_i;
Expand Down Expand Up @@ -406,7 +406,7 @@ module load_store_unit
AMO_SWAPD, AMO_ADDD, AMO_ANDD, AMO_ORD,
AMO_XORD, AMO_MAXD, AMO_MAXDU, AMO_MIND,
AMO_MINDU: begin
if (lsu_ctrl.vaddr[2:0] != 3'b000) begin
if (riscv::IS_XLEN64 && lsu_ctrl.vaddr[2:0] != 3'b000) begin
data_misaligned = 1'b1;
end
end
Expand Down
4 changes: 2 additions & 2 deletions core/mult.sv
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Expand Up @@ -89,7 +89,7 @@ module mult
// we've go a new division operation
if (mult_valid_i && fu_data_i.operation inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin
// is this a word operation?
if (fu_data_i.operation inside {DIVW, DIVUW, REMW, REMUW}) begin
if (riscv::IS_XLEN64 && (fu_data_i.operation inside {DIVW, DIVUW, REMW, REMUW})) begin
// yes so check if we should sign extend this is only done for a signed operation
if (div_signed) begin
operand_a = sext32(fu_data_i.operand_a[31:0]);
Expand Down Expand Up @@ -134,7 +134,7 @@ module mult

// Result multiplexer
// if it was a signed word operation the bit will be set and the result will be sign extended accordingly
assign div_result = (word_op_q) ? sext32(result) : result;
assign div_result = (riscv::IS_XLEN64 && word_op_q) ? sext32(result) : result;

// ---------------------
// Registers
Expand Down
6 changes: 4 additions & 2 deletions core/multiplier.sv
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Expand Up @@ -116,12 +116,14 @@ module multiplier
always_comb begin : p_selmux
unique case (operator_q)
MULH, MULHU, MULHSU: result_o = mult_result_q[riscv::XLEN*2-1:riscv::XLEN];
MULW: result_o = sext32(mult_result_q[31:0]);
CLMUL: result_o = clmul_q;
CLMULH: result_o = clmulr_q >> 1;
CLMULR: result_o = clmulr_q;
// MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register
default: result_o = mult_result_q[riscv::XLEN-1:0]; // including MUL
default: begin
if (operator_q == MULW && riscv::IS_XLEN64) result_o = sext32(mult_result_q[31:0]);
else result_o = mult_result_q[riscv::XLEN-1:0]; // including MUL
end
endcase
end
if (ariane_pkg::BITMANIP) begin
Expand Down