Code_coverage: condition RTL with the IS_XLEN64 parameter #1666
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Signed-off-by: Alae-Eddine Ez-Zejjari <[email protected]>
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| @@ -284,9 +284,6 @@ module alu | |||
| endcase | |||
| end | |||
| unique case (fu_data_i.operation) | |||
| // Left Shift 32 bit unsigned | |||
| SLLIUW: | |||
| result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; | |||
| // Integer minimum/maximum | |||
| MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; | |||
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| MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; | |
| MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; |
core/alu.sv
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| default: ; // default case to suppress unique warning | ||
| // Left Shift 32 bit unsigned | ||
| default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning |
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning | |
| default: | |
| if (fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) | |
| result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning |
| @@ -205,7 +205,7 @@ module wt_axi_adapter | |||
| 2'b10: | |||
| axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = '1; // word | |||
| default: | |||
| axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword | |||
| if (riscv::IS_XLEN64) axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword | |||
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| if (riscv::IS_XLEN64) axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword | |
| if (riscv::IS_XLEN64) | |
| axi_wr_be[0][dcache_data.paddr[$clog2( | |
| CVA6Cfg.AxiDataWidth/8 | |
| )-1:0]+:8] = '1; // dword |
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Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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core/alu.sv
Outdated
| @@ -344,7 +341,7 @@ module alu | |||
| ORCB: result_o = orcbw_result; | |||
| REV8: result_o = rev8w_result; | |||
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| default: ; // default case to suppress unique warning | |||
| default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned | |||
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[verible-verilog-format] reported by reviewdog 🐶
Suggested change
| default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned | |
| default: | |
| if (fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) | |
| result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned |
|
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1 similar comment
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Condition RTL with IS_XLEN64 parameter to identify the dead code and remove the dead gates from netlist.
Based on if() directives, VCS is able to identify the unused code, this will allow to improuve code coverage.