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Update CVA6 Architecture overview Figure #1488

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Oct 2, 2023
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Update CVA6 Architecture overview Figure #1488

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873d55c
Update CVA6 Architecture overview image
YazanHussnain-10x Sep 28, 2023
c88c29f
Vector File added of Ariane overview
YazanHussnain-10x Sep 30, 2023
141be21
Update the figure and add vector file
YazanHussnain-10x Oct 2, 2023
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2 changes: 1 addition & 1 deletion docs/03_cva6_design/intro.rst
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Expand Up @@ -10,5 +10,5 @@ Scope and Purpose
The purpose of the core is to run a full OS at reasonable speed and IPC. To achieve the necessary speed the core features a 6-stage pipelined design. In order to increase the IPC the CPU features a scoreboard which should hide latency to the data RAM (cache) by issuing data-independent instructions.
The instruction RAM has (or L1 instruction cache) an access latency of 1 cycle on a hit, while accesses to the data RAM (or L1 data cache) have a longer latency of 3 cycles on a hit.

.. image:: _static/ariane_overview.png
.. image:: _static/ariane_overview.drawio.png
:alt: Ariane Block Diagram
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2 changes: 1 addition & 1 deletion docs/04_cv32a6_design/source/cv32a6_intro.rst
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Expand Up @@ -26,7 +26,7 @@ This document is not dedicated to CVA6 users looking for information to develop

The CVA6 architecture is illustrated in the following figure extracted from a paper written by F.Zaruba and L.Benini.

.. figure:: ../images/ariane_overview.png
.. figure:: ../images/ariane_overview.drawio.png
:name: CVA6 Architecute
:align: center
:alt:
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