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try fixing swird split issues
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AngelaGonzalezMarino committed Dec 19, 2023
1 parent d26612f commit 2a01bd1
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions core/mmu_unify/cva6_ptw.sv
Original file line number Diff line number Diff line change
Expand Up @@ -185,8 +185,8 @@ module cva6_ptw
);


assign req_port_o.data_be = (riscv::XLEN == 32) ?
be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size) :
assign req_port_o.data_be = (riscv::XLEN == 32) ? //
be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size) : //
be_gen(req_port_o.address_index[2:0], req_port_o.data_size);

//-------------------
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