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Code_coverage: condition RTL with the U-MODE parameter (#1583) ci #1612: Commit d92f0f7 pushed by JeanRochCoulon
October 31, 2023 12:46 1h 10m 34s master
master
October 31, 2023 12:46 1h 10m 34s
Code_coverage: condition RTL with the U-MODE parameter ci #1611: Pull request #1583 opened by AEzzejjari
October 31, 2023 11:50 2h 1m 14s ThalesSiliconSecurity:UMODE_Delete
ThalesSiliconSecurity:UMODE_Delete
October 31, 2023 11:50 2h 1m 14s
Code_coverage: condition RTL with the debug parameter ci #1610: Pull request #1582 opened by AEzzejjari
October 31, 2023 11:49 24m 59s ThalesSiliconSecurity:Debug_Delete
ThalesSiliconSecurity:Debug_Delete
October 31, 2023 11:49 24m 59s
Add funding acknowledgement ci #1609: Pull request #1581 synchronize by jquevremont
October 31, 2023 10:10 2h 23m 11s jquevremont-acknowledgement
jquevremont-acknowledgement
October 31, 2023 10:10 2h 23m 11s
Add funding acknowledgement ci #1608: Pull request #1581 synchronize by JeanRochCoulon
October 31, 2023 10:03 2h 27m 55s jquevremont-acknowledgement
jquevremont-acknowledgement
October 31, 2023 10:03 2h 27m 55s
conditioned RTL with XLEN parameter ci #1607: Pull request #1579 synchronize by fatimasaleem
October 31, 2023 09:48 2h 7m 16s 10x-Engineers:xlen-param
10x-Engineers:xlen-param
October 31, 2023 09:48 2h 7m 16s
conditioned RTL with XLEN parameter ci #1606: Pull request #1579 synchronize by fatimasaleem
October 31, 2023 09:46 1h 24m 38s 10x-Engineers:xlen-param
10x-Engineers:xlen-param
October 31, 2023 09:46 1h 24m 38s
Add funding acknowledgement ci #1605: Pull request #1581 opened by jquevremont
October 31, 2023 09:32 1h 52m 28s jquevremont-acknowledgement
jquevremont-acknowledgement
October 31, 2023 09:32 1h 52m 28s
Reduce the number of executed tests (#1580) ci #1604: Commit 18e9d8e pushed by JeanRochCoulon
October 31, 2023 08:36 1h 14m 32s master
master
October 31, 2023 08:36 1h 14m 32s
Reduce the number of executed tests ci #1603: Pull request #1580 opened by JeanRochCoulon
October 31, 2023 05:59 1h 15m 28s JeanRochCoulon-patch-3
JeanRochCoulon-patch-3
October 31, 2023 05:59 1h 15m 28s
Reduce the number of executed tests ci #1602: Commit 92e954f pushed by JeanRochCoulon
October 31, 2023 05:59 1h 56m 53s JeanRochCoulon-patch-3
JeanRochCoulon-patch-3
October 31, 2023 05:59 1h 56m 53s
conditioned RTL with XLEN parameter ci #1601: Pull request #1579 opened by fatimasaleem
October 30, 2023 20:26 1h 58m 56s 10x-Engineers:xlen-param
10x-Engineers:xlen-param
October 30, 2023 20:26 1h 58m 56s
Generate illegal exception when accessing CSR Trigger CSRs (#1577) ci #1600: Commit 73a6b84 pushed by JeanRochCoulon
October 30, 2023 16:08 1h 26m 23s master
master
October 30, 2023 16:08 1h 26m 23s
Generate illegal exception when accessing CSR Trigger CSRs ci #1599: Pull request #1577 opened by JeanRochCoulon
October 30, 2023 13:35 1h 46m 29s JeanRochCoulon-patch-3
JeanRochCoulon-patch-3
October 30, 2023 13:35 1h 46m 29s
Generate illegal exception when accessing CSR Trigger CSRs ci #1598: Commit 646571c pushed by JeanRochCoulon
October 30, 2023 13:35 1h 50m 7s JeanRochCoulon-patch-3
JeanRochCoulon-patch-3
October 30, 2023 13:35 1h 50m 7s
Updates to match the latest version of RISCV-DV (#1576) ci #1597: Commit e2a5250 pushed by JeanRochCoulon
October 30, 2023 13:11 1h 14m 52s master
master
October 30, 2023 13:11 1h 14m 52s
Updates to match the latest version of RISCV-DV ci #1596: Pull request #1576 synchronize by AyoubJalali
October 30, 2023 12:35 1h 44m 55s ThalesSiliconSecurity:update-dv
ThalesSiliconSecurity:update-dv
October 30, 2023 12:35 1h 44m 55s
cva6_icache: Allow one outstanding killed miss ci #1595: Pull request #1497 synchronize by colluca
October 30, 2023 11:50 1h 15m 56s colluca:feature/async-kill-miss
colluca:feature/async-kill-miss
October 30, 2023 11:50 1h 15m 56s
Updates to match the latest version of RISCV-DV ci #1594: Pull request #1576 opened by AyoubJalali
October 30, 2023 10:11 1h 57m 2s ThalesSiliconSecurity:update-dv
ThalesSiliconSecurity:update-dv
October 30, 2023 10:11 1h 57m 2s
Code_coverage: condition RTL with the S-MODE parameter (#1574) ci #1593: Commit 4b67475 pushed by JeanRochCoulon
October 27, 2023 20:38 1h 26m 56s master
master
October 27, 2023 20:38 1h 26m 56s
Spike Tandem Implementation using VCS simulator ci #1592: Pull request #1561 synchronize by MarioOpenHWGroup
October 27, 2023 12:46 2h 2m 23s MarioOpenHWGroup:1402-1403/spike-tandem
MarioOpenHWGroup:1402-1403/spike-tandem
October 27, 2023 12:46 2h 2m 23s
Spike Tandem Implementation using VCS simulator ci #1591: Pull request #1561 synchronize by MarioOpenHWGroup
October 27, 2023 11:26 43m 30s MarioOpenHWGroup:1402-1403/spike-tandem
MarioOpenHWGroup:1402-1403/spike-tandem
October 27, 2023 11:26 43m 30s
Code_coverage: condition RTL with the S-MODE parameter ci #1590: Pull request #1574 synchronize by JeanRochCoulon
October 27, 2023 11:12 1h 15m 59s ThalesSiliconSecurity:SMODE_Delete
ThalesSiliconSecurity:SMODE_Delete
October 27, 2023 11:12 1h 15m 59s
Spike Tandem Implementation using VCS simulator ci #1589: Pull request #1561 synchronize by MarioOpenHWGroup
October 26, 2023 22:48 1h 40m 56s MarioOpenHWGroup:1402-1403/spike-tandem
MarioOpenHWGroup:1402-1403/spike-tandem
October 26, 2023 22:48 1h 40m 56s
Spike Tandem Implementation using VCS simulator ci #1588: Pull request #1561 synchronize by MarioOpenHWGroup
October 26, 2023 17:54 1h 1m 19s MarioOpenHWGroup:1402-1403/spike-tandem
MarioOpenHWGroup:1402-1403/spike-tandem
October 26, 2023 17:54 1h 1m 19s