[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/alu.sv:323:- ORCB: core/alu.sv:324:- result_o = orcbw_result; core/alu.sv:325:- REV8: core/alu.sv:326:- result_o = rev8w_result; core/alu.sv:346:+ ORCB: result_o = orcbw_result; core/alu.sv:347:+ REV8: result_o = rev8w_result;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cache_subsystem/cache_ctrl.sv:84:- logic [DCACHE_TID_WIDTH-1:0] id; core/cache_subsystem/cache_ctrl.sv:85:- logic [7:0] be; core/cache_subsystem/cache_ctrl.sv:86:- logic [1:0] size; core/cache_subsystem/cache_ctrl.sv:87:- logic we; core/cache_subsystem/cache_ctrl.sv:88:- logic [63:0] wdata; core/cache_subsystem/cache_ctrl.sv:89:- logic bypass; core/cache_subsystem/cache_ctrl.sv:90:- logic killed; core/cache_subsystem/cache_ctrl.sv:84:+ logic [DCACHE_TID_WIDTH-1:0] id; core/cache_subsystem/cache_ctrl.sv:85:+ logic [7:0] be; core/cache_subsystem/cache_ctrl.sv:86:+ logic [1:0] size; core/cache_subsystem/cache_ctrl.sv:87:+ logic we; core/cache_subsystem/cache_ctrl.sv:88:+ logic [63:0] wdata; core/cache_subsystem/cache_ctrl.sv:89:+ logic bypass; core/cache_subsystem/cache_ctrl.sv:90:+ logic killed;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cache_subsystem/wt_axi_adapter.sv:217:- if(CVA6Cfg.RVA) begin core/cache_subsystem/wt_axi_adapter.sv:218:- // default core/cache_subsystem/wt_axi_adapter.sv:219:- // push back an invalidation here. core/cache_subsystem/wt_axi_adapter.sv:220:- // since we only keep one read tx in flight, and since core/cache_subsystem/wt_axi_adapter.sv:221:- // the dcache drains all writes/reads before executing core/cache_subsystem/wt_axi_adapter.sv:222:- // an atomic, this is safe. core/cache_subsystem/wt_axi_adapter.sv:223:- invalidate = arb_gnt; core/cache_subsystem/wt_axi_adapter.sv:224:- axi_wr_req = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:225:- axi_wr_be = '0; core/cache_subsystem/wt_axi_adapter.sv:226:- unique case(dcache_data.size[1:0]) core/cache_subsystem/wt_axi_adapter.sv:227:- 2'b00: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]] = '1; // byte core/cache_subsystem/wt_axi_adapter.sv:228:- 2'b01: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:2 ] = '1; // hword core/cache_subsystem/wt_axi_adapter.sv:229:- 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:4 ] = '1; // word core/cache_subsystem/wt_axi_adapter.sv:230:- default: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] +:8 ] = '1; // dword core/cache_subsystem/wt_axi_adapter.sv:231:- endcase core/cache_subsystem/wt_axi_adapter.sv:232:- amo_gen_r_d = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:233:- // need to use a separate ID here, so concat an additional bit core/cache_subsystem/wt_axi_adapter.sv:234:- axi_wr_id_in[1] = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:235:- core/cache_subsystem/wt_axi_adapter.sv:236:- unique case (dcache_data.amo_op) core/cache_subsystem/wt_axi_adapter.sv:237:- AMO_LR: begin core/cache_subsystem/wt_axi_adapter.sv:238:- axi_rd_lock = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:239:- axi_rd_req = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:240:- axi_rd_id_in[1] = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:241:- // tie to zero in this special case core/cache_subsystem/wt_axi_adapter.sv:242:- axi_wr_req = 1'b0; core/cache_subsystem/wt_axi_adapter.sv:243:- axi_wr_be = '0; core/cache_subsystem/wt_axi_adapter.sv:244:- end core/cache_subsystem/wt_axi_adapter.sv:245:- AMO_SC: begin core/cache_subsystem/wt_axi_adapter.sv:246:- axi_wr_lock = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:247:- amo_gen_r_d = 1'b0; core/cache_subsystem/wt_axi_adapter.sv:248:- // needed to properly encode success. store the result at offset within the returned core/cache_subsystem/wt_axi_adapter.sv:249:- // AXI data word aligned with the requested word size. core/cache_subsystem/wt_axi_adapter.sv:250:- amo_off_d = dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0] & ~((1 << dcache_data.size[1:0]) - 1); core/cache_subsystem/wt_axi_adapter.sv:251:- end core/cache_subsystem/wt_axi_adapter.sv:252:- // RISC-V atops have a load semantic core/cache_subsystem/wt_axi_adapter.sv:253:- AMO_SWAP: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ATOMICSWAP}; core/cache_subsystem/wt_axi_adapter.sv:254:- AMO_ADD: axi_wr_atop = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; core/cache_subsystem/wt_axi_adapter.sv:255:- AMO_AND: begin core/cache_subsystem/wt_axi_adapter.sv:256:- // in this case we need to invert the data

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cache_subsystem/wt_axi_adapter.sv:533:- dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ; core/cache_subsystem/wt_axi_adapter.sv:534:- dcache_rtrn_vld_d = 1'b1; core/cache_subsystem/wt_axi_adapter.sv:567:+ dcache_rtrn_type_d = wt_cache_pkg::DCACHE_INV_REQ; core/cache_subsystem/wt_axi_adapter.sv:568:+ dcache_rtrn_vld_d = 1'b1;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cva6.sv:471:- logic we_csr_perf; core/cva6.sv:472:- core/cva6.sv:473:- logic icache_flush_ctrl_cache; core/cva6.sv:474:- logic itlb_miss_ex_perf; core/cva6.sv:475:- logic dtlb_miss_ex_perf; core/cva6.sv:476:- logic dcache_miss_cache_perf; core/cva6.sv:477:- logic icache_miss_cache_perf; core/cva6.sv:478:- logic [ NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits; core/cva6.sv:479:- logic stall_issue; core/cva6.sv:471:+ logic we_csr_perf; core/cva6.sv:472:+ core/cva6.sv:473:+ logic icache_flush_ctrl_cache; core/cva6.sv:474:+ logic itlb_miss_ex_perf; core/cva6.sv:475:+ logic dtlb_miss_ex_perf; core/cva6.sv:476:+ logic dcache_miss_cache_perf; core/cva6.sv:477:+ logic icache_miss_cache_perf; core/cva6.sv:478:+ logic [NumPorts-1:0][CVA6Cfg.DCACHE_SET_ASSOC-1:0] miss_vld_bits; core/cva6.sv:479:+ logic stall_issue;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cva6.sv:514:- dcache_req_i_t [ 2:0] dcache_req_ports_ex_cache; core/cva6.sv:515:- dcache_req_o_t [ 2:0] dcache_req_ports_cache_ex; core/cva6.sv:516:- dcache_req_i_t [ 1:0] dcache_req_ports_acc_cache; core/cva6.sv:517:- dcache_req_o_t [ 1:0] dcache_req_ports_cache_acc; core/cva6.sv:518:- logic dcache_commit_wbuffer_empty; core/cva6.sv:519:- logic dcache_commit_wbuffer_not_ni; core/cva6.sv:520:- core/cva6.sv:521:- logic [ CVA6Cfg.VLEN-1:0] lsu_addr; core/cva6.sv:522:- logic [ CVA6Cfg.PLEN-1:0] mem_paddr; core/cva6.sv:523:- logic [ (CVA6Cfg.XLEN/8)-1:0] lsu_rmask; core/cva6.sv:524:- logic [ (CVA6Cfg.XLEN/8)-1:0] lsu_wmask; core/cva6.sv:525:- logic [CVA6Cfg.TRANS_ID_BITS-1:0] lsu_addr_trans_id; core/cva6.sv:514:+ dcache_req_i_t [2:0] dcache_req_ports_ex_cache; core/cva6.sv:515:+ dcache_req_o_t [2:0] dcache_req_ports_cache_ex; core/cva6.sv:516:+ dcache_req_i_t [1:0] dcache_req_ports_acc_cache; core/cva6.sv:517:+ dcache_req_o_t [1:0] dcache_req_ports_cache_acc; core/cva6.sv:518:+ logic dcache_commit_wbuffer_empty; core/cva6.sv:519:+ logic dcache_commit_wbuffer_not_ni; core/cva6.sv:520:+ core/cva6.sv:521:+ logic [CVA6Cfg.VLEN-1:0] lsu_addr; core/cva6.sv:522:+ logic [CVA6Cfg.PLEN-1:0] mem_paddr; core/cva6.sv:523:+ logic [(CVA6Cfg.XLEN/8)-1:0] lsu_rmask; core/cva6.sv:524:+ logic [(CVA6Cfg.XLEN/8)-1:0] lsu_wmask; core/cva6.sv:525:+ logic [CVA6Cfg.TRANS_ID_BITS-1:0] lsu_addr_trans_id;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cva6.sv:528:- logic [ 63:0] inval_addr; core/cva6.sv:529:- logic inval_valid; core/cva6.sv:530:- logic inval_ready; core/cva6.sv:528:+ logic [63:0] inval_addr; core/cva6.sv:529:+ logic inval_valid; core/cva6.sv:530:+ logic inval_ready;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cva6.sv:1216:- .NumPorts (NumPorts), core/cva6.sv:1217:- .axi_ar_chan_t(axi_ar_chan_t), core/cva6.sv:1218:- .axi_aw_chan_t(axi_aw_chan_t), core/cva6.sv:1219:- .axi_w_chan_t (axi_w_chan_t), core/cva6.sv:1220:- .axi_req_t (noc_req_t), core/cva6.sv:1221:- .axi_rsp_t (noc_resp_t) core/cva6.sv:1216:+ .NumPorts (NumPorts), core/cva6.sv:1217:+ .axi_ar_chan_t (axi_ar_chan_t), core/cva6.sv:1218:+ .axi_aw_chan_t (axi_aw_chan_t), core/cva6.sv:1219:+ .axi_w_chan_t (axi_w_chan_t), core/cva6.sv:1220:+ .axi_req_t (noc_req_t), core/cva6.sv:1221:+ .axi_rsp_t (noc_resp_t)

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/cva6.sv:1266:- .dcache_req_i_t(dcache_req_i_t), core/cva6.sv:1267:- .dcache_req_o_t(dcache_req_o_t), core/cva6.sv:1268:- .acc_cfg_t (acc_cfg_t), core/cva6.sv:1269:- .AccCfg (AccCfg), core/cva6.sv:1270:- .acc_req_t (cvxif_req_t), core/cva6.sv:1271:- .acc_resp_t(cvxif_resp_t) core/cva6.sv:1266:+ .dcache_req_i_t (dcache_req_i_t), core/cva6.sv:1267:+ .dcache_req_o_t (dcache_req_o_t), core/cva6.sv:1268:+ .acc_cfg_t (acc_cfg_t), core/cva6.sv:1269:+ .AccCfg (AccCfg), core/cva6.sv:1270:+ .acc_req_t (cvxif_req_t), core/cva6.sv:1271:+ .acc_resp_t (cvxif_resp_t)