Special Project on Application Acceleration with High-Level Synthesis

This repository was created for the course Application Acceleration with High-Level Synthesis, offered by NTU in the Fall 2024 semester. The course is taught by Professor Jiin Lai.

For more information, please visit:

• Personal website
• GitHub profile

Course Overview

The course consists of four laboratory sessions and a final project:

1. Lab 1 & Lab 2
   These are straightforward examples that follow the tutorial provided in the corresponding Lab 2 repository.

2. Lab 3
   This session uses the Xilinx Alveo U50 FPGA board to develop an application accelerator using OpenCL.

3. Lab A & Lab B
   These sessions allow students to choose from a given set of options.

   • Lab A: I chose to follow the Vitis HLS tutorial on dataflow optimization and deadlock debugging.
     Lab A repository
   • Lab B: I chose to implement a matrix multiplication accelerator.
     Lab B repository

Final Project

For the final project, we formed a group to design and implement a complete system, including host software and a hardware kernel, for a Vision Transformer (ViT) accelerator.
Final Project Repository

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Additional details about each lab and project can be found in the README.md files within the respective folders.